add_2bit_module.twr

该源码为xilinx ise教程的附带光盘源码

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Release 9.1i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

D:\Xilinx91i\bin\nt\trce.exe -ise D:/ise_book/Example-8-2/test_add/test_add.ise
-intstyle ise -e 3 -s 6 -xml add_2bit_module add_2bit_module.ncd -o
add_2bit_module.twr add_2bit_module.pcf

Design file:              add_2bit_module.ncd
Physical constraint file: add_2bit_module.pcf
Device,package,speed:     xcv50e,cs144,-6 (PRODUCTION 1.69 2006-10-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
a<0>           |c<0>           |    8.645|
a<0>           |c<1>           |    8.406|
a<0>           |cout           |    8.254|
a<1>           |c<1>           |    9.221|
a<1>           |cout           |    9.757|
b<0>           |c<0>           |    8.666|
b<1>           |c<1>           |    8.242|
b<1>           |cout           |    8.778|
cin            |c<0>           |    8.387|
cin            |c<1>           |    8.197|
cin            |cout           |    8.045|
---------------+---------------+---------+


Analysis completed Wed Dec 27 17:40:20 2006
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 81 MB