add_2bit_fpga_editor.scr

该源码为xilinx ise教程的附带光盘源码

#:C69    
#Xilinx FPGA Editor Command Log File
#Editor Version:
#:V   NT M2.1 1.0
#Design Path Name:
#:N   add_2bit.nmc
#Current Working Directory:
#:D   E:\work_dir\add_2bit
#Part Type:
#:P  Xilinx xcv50e cs144 -6
#Date/Time:
#:T   Sun Dec 29 11:07:10 2002
#------------------------------
	#1
setattr main disable_draw on
	#2
setattr layer switch_boxes view on
	#3
setattr main disable_draw off
	#Hint: change the visibility of more than one layer at a time by clicking on the apply button, clicking two or more layer buttons, and then clicking on the apply button again.
	#4
unselect -all
	#5
select site "CLB_R9C6.S0"
	#site "CLB_R9C6.S0",  type = SLICE
	#6
unselect -all
	#7
select site "CLB_R9C5.S0"
	#site "CLB_R9C5.S0",  type = SLICE
	#8
unselect -all
	#9
select site "CLB_R8C5.S0"
	#site "CLB_R8C5.S0",  type = SLICE
	#10
unselect -all
	#11
select site "CLB_R8C3.S0"
	#site "CLB_R8C3.S0",  type = SLICE
	#12
unselect -all
	#13
select site "CLB_R8C2.S0"
	#site "CLB_R8C2.S0",  type = SLICE
	#14
add
	#15
post attr comp $COMP_0
	#16
setattr comp $COMP_0  Name SLICE1
	#17
unpost comp "SLICE1"
	#18
unselect -all
	#19
unselect -all
	#20
select pin "CLB_R8C2.S0.F1"
	#site.pin = CLB_R8C2.S0.F1, comp.pin = SLICE1.F1
	#21
add extpin
	#22
post attr pin CLB_R8C2.S0.F1
	#23
setattr pin CLB_R8C2.S0.F1  external_name A[0]
	#24
unpost pin "CLB_R8C2.S0.F1"
	#25
unselect -all
	#26
select pin "CLB_R8C2.S0.F2"
	#site.pin = CLB_R8C2.S0.F2, comp.pin = SLICE1.F2
	#27
add extpin
	#28
post attr pin CLB_R8C2.S0.F2
	#29
setattr pin CLB_R8C2.S0.F2  external_name b[0]
	#30
unpost pin "CLB_R8C2.S0.F2"
	#31
unselect -all
	#32
select pin "CLB_R8C2.S0.G1"
	#site.pin = CLB_R8C2.S0.G1, comp.pin = SLICE1.G1
	#33
add extpin
	#34
post attr pin CLB_R8C2.S0.G1
	#35
setattr pin CLB_R8C2.S0.G1  external_name a[1]
	#36
unpost pin "CLB_R8C2.S0.G1"
	#37
unselect -all
	#38
select pin "CLB_R8C2.S0.G2"
	#site.pin = CLB_R8C2.S0.G2, comp.pin = SLICE1.G2
	#39
add extpin
	#40
post attr pin CLB_R8C2.S0.G2
	#41
setattr pin CLB_R8C2.S0.G2  external_name b[1]
	#42
unpost pin "CLB_R8C2.S0.G2"
	#43
unselect -all
	#44
select pin "CLB_R8C2.S0.CIN"
	#site.pin = CLB_R8C2.S0.CIN, comp.pin = SLICE1.CIN
	#45
add extpin
	#46
post attr pin CLB_R8C2.S0.CIN
	#47
setattr pin CLB_R8C2.S0.CIN  external_name cin
	#48
unpost pin "CLB_R8C2.S0.CIN"
	#49
unselect -all
	#50
select pin "CLB_R8C2.S0.COUT"
	#site.pin = CLB_R8C2.S0.COUT, comp.pin = SLICE1.COUT
	#51
add extpin
	#52
post attr pin CLB_R8C2.S0.COUT
	#53
setattr pin CLB_R8C2.S0.COUT  external_name cout
	#54
unpost pin "CLB_R8C2.S0.COUT"
	#55
unselect -all
	#56
select pin "CLB_R8C2.S0.X"
	#site.pin = CLB_R8C2.S0.X, comp.pin = SLICE1.X
	#57
add extpin
	#58
post attr pin CLB_R8C2.S0.X
	#59
setattr pin CLB_R8C2.S0.X  external_name c[0]
	#60
unpost pin "CLB_R8C2.S0.X"
	#61
unselect -all
	#62
select pin "CLB_R8C2.S0.Y"
	#site.pin = CLB_R8C2.S0.Y, comp.pin = SLICE1.Y
	#63
add extpin
	#64
post attr pin CLB_R8C2.S0.Y
	#65
setattr pin CLB_R8C2.S0.Y  external_name c[1]
	#66
unpost pin "CLB_R8C2.S0.Y"
	#67
unselect -all
	#68
select comp "SLICE1"
	#comp "SLICE1",  site "CLB_R8C2.S0",  type = SLICE
	#69
editblock
	#70
setattr comp SLICE1 F (A1@A2)
	#71
setattr comp SLICE1 G (A1@A2)
	#WARNING:DesignRules:331 - Blockcheck: Dangling F output. F of comp SLICE1 is configured, but output is not used.
	#WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp SLICE1 is configured, but output is not used.
	#WARNING:DesignRules:339 - Blockcheck: Useless input pin. Pin CIN of comp SLICE1 is connected, but CYINIT does not use it.
	#WARNING:DesignRules:341 - Blockcheck: Useless output pin. Pin COUT of comp SLICE1 is connected, but COUTUSED does not source it.
	#WARNING:DesignRules:341 - Blockcheck: Useless output pin. Pin Y of comp SLICE1 is connected, but YUSED does not source it.
	#WARNING:DesignRules:341 - Blockcheck: Useless output pin. Pin X of comp SLICE1 is connected, but XUSED does not source it.
	#DRC - comp check: 6 warnings, 0 errors.
	#0 DRC errors and 6 DRC warnings.
	#72
block restore
	#73
setattr comp SLICE1 F (A1@A2)
	#74
setattr comp SLICE1 G (A1@A2)
	#WARNING:DesignRules:331 - Blockcheck: Dangling F output. F of comp SLICE1 is configured, but output is not used.
	#WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp SLICE1 is configured, but output is not used.
	#WARNING:DesignRules:339 - Blockcheck: Useless input pin. Pin CIN of comp SLICE1 is connected, but CYINIT does not use it.
	#WARNING:DesignRules:341 - Blockcheck: Useless output pin. Pin COUT of comp SLICE1 is connected, but COUTUSED does not source it.
	#WARNING:DesignRules:341 - Blockcheck: Useless output pin. Pin Y of comp SLICE1 is connected, but YUSED does not source it.
	#WARNING:DesignRules:341 - Blockcheck: Useless output pin. Pin X of comp SLICE1 is connected, but XUSED does not source it.
	#DRC - comp check: 6 warnings, 0 errors.
	#0 DRC errors and 6 DRC warnings.
	#<CYINIT>.
	#<XORF>.
	#<XORF>.
	#<CYMUXG>.
	#<CYMUXF>.
	#<CYMUXF>.
	#<CYMUXF>.
	#<CYSELF>.
	#<CYMUXF>.
	#<CYMUXF>.
	#<COUTUSED>.
	#<CYSELG>.
	#<YUSED>.
	#<YUSED>.
	#<YUSED>.
	#<GYMUX>.
	#<CY0G>.
	#<CY0F>.
	#<XUSED>.
	#<FXMUX>.
	#75
save
	#Component "SLICE1" assigned to be reference component.