counter.v

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    08:41:49 06/25/2006 
// Design Name: 
// Module Name:    counter 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module counter(clk, rst_n, direction, cnt_out);
    input clk;
    input rst_n;
    input direction;
    output [15:0] cnt_out;

  reg [37:0] cnt;
  always @(posedge clk)
    if (!rst_n )
		  cnt <= 0;
    else if ( direction )
		  cnt <= cnt + 1;
    else
      cnt <= cnt - 1;			
      
	assign cnt_out = cnt[37:22];
						
endmodule