run5_map.mrp

该源码为xilinx ise教程的附带光盘源码

Release 9.1i Map J.30
Xilinx Mapping Report File for Design 'counter'

Design Information
------------------
Command Line   : D:\Xilinx91i\bin\nt\map.exe -p xc3s400-4pq208 -timing -ol high
-xe n D:/ise_book/Example-4-1/xplorer/counter.ngd -o
D:/ise_book/Example-4-1/xplorer/run5_map.ncd
D:/ise_book/Example-4-1/xplorer/run5.pcf 
Target Device  : xc3s400
Target Package : pq208
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.36 $
Mapped Date    : Tue Dec 12 08:58:31 2006

Design Summary
--------------
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:          38 out of   7,168    1%
  Number of 4 input LUTs:              38 out of   7,168    1%
Logic Distribution:
  Number of occupied Slices:                           19 out of   3,584    1%
    Number of Slices containing only related logic:      19 out of      19  100%
    Number of Slices containing unrelated logic:          0 out of      19    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:          38 out of   7,168    1%
  Number of bonded IOBs:               19 out of     141   13%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  760
Additional JTAG gate count for IOBs:  912
Peak Memory Usage:  165 MB
Total REAL time to MAP completion:  9 secs 
Total CPU time to MAP completion:   9 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network N1 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
   more times for the following (max. 5 shown):
   N2
   To see the details of these warning messages, please use the -detail switch.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:863 - The following Virtex BUFG(s) is/are being retargeted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
INFO:Pack:1650 - Map created a placed design.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) removed
   2 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "N1" is loadless and has been removed.
 Loadless block "XST_GND" (ZERO) removed.
The signal "N2" is loadless and has been removed.
 Loadless block "XST_VCC" (ONE) removed.

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| cnt_out<0>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<1>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<2>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<3>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<4>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<5>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<6>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<7>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<8>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<9>                         | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<10>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<11>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<12>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<13>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<14>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| cnt_out<15>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| direction                          | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| rst_n                              | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.


----------------------

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
INFO:Timing:3284 - This timing report was generated using estimated delay 
   information.  For accurate numbers, please refer to the post Place and Route 
   timing report.
Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 5.59218559  | SETUP   |     0.133ns|     5.459ns|       0|           0
  ns HIGH 50%                               | HOLD    |     1.612ns|            |       0|           0
------------------------------------------------------------------------------------------------------


All constraints were met.



Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings