📄 run1.twr
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SLICE_X54Y14.CIN net (fanout=1) 0.000 Mcount_cnt_cy<3>
SLICE_X54Y14.COUT Tbyp 0.120 cnt<4>
Mcount_cnt_cy<4>
Mcount_cnt_cy<5>
SLICE_X54Y15.CIN net (fanout=1) 0.000 Mcount_cnt_cy<5>
SLICE_X54Y15.COUT Tbyp 0.120 cnt<6>
Mcount_cnt_cy<6>
Mcount_cnt_cy<7>
SLICE_X54Y16.CIN net (fanout=1) 0.000 Mcount_cnt_cy<7>
SLICE_X54Y16.COUT Tbyp 0.120 cnt<8>
Mcount_cnt_cy<8>
Mcount_cnt_cy<9>
SLICE_X54Y17.CIN net (fanout=1) 0.000 Mcount_cnt_cy<9>
SLICE_X54Y17.COUT Tbyp 0.120 cnt<10>
Mcount_cnt_cy<10>
Mcount_cnt_cy<11>
SLICE_X54Y18.CIN net (fanout=1) 0.000 Mcount_cnt_cy<11>
SLICE_X54Y18.COUT Tbyp 0.120 cnt<12>
Mcount_cnt_cy<12>
Mcount_cnt_cy<13>
SLICE_X54Y19.CIN net (fanout=1) 0.000 Mcount_cnt_cy<13>
SLICE_X54Y19.COUT Tbyp 0.120 cnt<14>
Mcount_cnt_cy<14>
Mcount_cnt_cy<15>
SLICE_X54Y20.CIN net (fanout=1) 0.000 Mcount_cnt_cy<15>
SLICE_X54Y20.COUT Tbyp 0.120 cnt<16>
Mcount_cnt_cy<16>
Mcount_cnt_cy<17>
SLICE_X54Y21.CIN net (fanout=1) 0.000 Mcount_cnt_cy<17>
SLICE_X54Y21.COUT Tbyp 0.120 cnt<18>
Mcount_cnt_cy<18>
Mcount_cnt_cy<19>
SLICE_X54Y22.CIN net (fanout=1) 0.000 Mcount_cnt_cy<19>
SLICE_X54Y22.COUT Tbyp 0.120 cnt<20>
Mcount_cnt_cy<20>
Mcount_cnt_cy<21>
SLICE_X54Y23.CIN net (fanout=1) 0.000 Mcount_cnt_cy<21>
SLICE_X54Y23.COUT Tbyp 0.120 cnt<22>
Mcount_cnt_cy<22>
Mcount_cnt_cy<23>
SLICE_X54Y24.CIN net (fanout=1) 0.000 Mcount_cnt_cy<23>
SLICE_X54Y24.COUT Tbyp 0.120 cnt<24>
Mcount_cnt_cy<24>
Mcount_cnt_cy<25>
SLICE_X54Y25.CIN net (fanout=1) 0.000 Mcount_cnt_cy<25>
SLICE_X54Y25.COUT Tbyp 0.120 cnt<26>
Mcount_cnt_cy<26>
Mcount_cnt_cy<27>
SLICE_X54Y26.CIN net (fanout=1) 0.000 Mcount_cnt_cy<27>
SLICE_X54Y26.COUT Tbyp 0.120 cnt<28>
Mcount_cnt_cy<28>
Mcount_cnt_cy<29>
SLICE_X54Y27.CIN net (fanout=1) 0.000 Mcount_cnt_cy<29>
SLICE_X54Y27.COUT Tbyp 0.120 cnt<30>
Mcount_cnt_cy<30>
Mcount_cnt_cy<31>
SLICE_X54Y28.CIN net (fanout=1) 0.000 Mcount_cnt_cy<31>
SLICE_X54Y28.CLK Tcinck 1.005 cnt<32>
Mcount_cnt_cy<32>
Mcount_cnt_xor<33>
cnt_33
------------------------------------------------- ---------------------------
Total 5.467ns (4.501ns logic, 0.966ns route)
(82.3% logic, 17.7% route)
--------------------------------------------------------------------------------
Slack: 1.835ns (requirement - (data path - clock path skew + uncertainty))
Source: cnt_7 (FF)
Destination: cnt_37 (FF)
Requirement: 7.321ns
Data Path Delay: 5.467ns (Levels of Logic = 16)
Clock Path Skew: -0.019ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 7.321ns
Clock Uncertainty: 0.000ns
Maximum Data Path: cnt_7 to cnt_37
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X54Y15.YQ Tcko 0.720 cnt<6>
cnt_7
SLICE_X54Y15.G1 net (fanout=1) 0.966 cnt<7>
SLICE_X54Y15.COUT Topcyg 1.096 cnt<6>
Mcount_cnt_lut<7>
Mcount_cnt_cy<7>
SLICE_X54Y16.CIN net (fanout=1) 0.000 Mcount_cnt_cy<7>
SLICE_X54Y16.COUT Tbyp 0.120 cnt<8>
Mcount_cnt_cy<8>
Mcount_cnt_cy<9>
SLICE_X54Y17.CIN net (fanout=1) 0.000 Mcount_cnt_cy<9>
SLICE_X54Y17.COUT Tbyp 0.120 cnt<10>
Mcount_cnt_cy<10>
Mcount_cnt_cy<11>
SLICE_X54Y18.CIN net (fanout=1) 0.000 Mcount_cnt_cy<11>
SLICE_X54Y18.COUT Tbyp 0.120 cnt<12>
Mcount_cnt_cy<12>
Mcount_cnt_cy<13>
SLICE_X54Y19.CIN net (fanout=1) 0.000 Mcount_cnt_cy<13>
SLICE_X54Y19.COUT Tbyp 0.120 cnt<14>
Mcount_cnt_cy<14>
Mcount_cnt_cy<15>
SLICE_X54Y20.CIN net (fanout=1) 0.000 Mcount_cnt_cy<15>
SLICE_X54Y20.COUT Tbyp 0.120 cnt<16>
Mcount_cnt_cy<16>
Mcount_cnt_cy<17>
SLICE_X54Y21.CIN net (fanout=1) 0.000 Mcount_cnt_cy<17>
SLICE_X54Y21.COUT Tbyp 0.120 cnt<18>
Mcount_cnt_cy<18>
Mcount_cnt_cy<19>
SLICE_X54Y22.CIN net (fanout=1) 0.000 Mcount_cnt_cy<19>
SLICE_X54Y22.COUT Tbyp 0.120 cnt<20>
Mcount_cnt_cy<20>
Mcount_cnt_cy<21>
SLICE_X54Y23.CIN net (fanout=1) 0.000 Mcount_cnt_cy<21>
SLICE_X54Y23.COUT Tbyp 0.120 cnt<22>
Mcount_cnt_cy<22>
Mcount_cnt_cy<23>
SLICE_X54Y24.CIN net (fanout=1) 0.000 Mcount_cnt_cy<23>
SLICE_X54Y24.COUT Tbyp 0.120 cnt<24>
Mcount_cnt_cy<24>
Mcount_cnt_cy<25>
SLICE_X54Y25.CIN net (fanout=1) 0.000 Mcount_cnt_cy<25>
SLICE_X54Y25.COUT Tbyp 0.120 cnt<26>
Mcount_cnt_cy<26>
Mcount_cnt_cy<27>
SLICE_X54Y26.CIN net (fanout=1) 0.000 Mcount_cnt_cy<27>
SLICE_X54Y26.COUT Tbyp 0.120 cnt<28>
Mcount_cnt_cy<28>
Mcount_cnt_cy<29>
SLICE_X54Y27.CIN net (fanout=1) 0.000 Mcount_cnt_cy<29>
SLICE_X54Y27.COUT Tbyp 0.120 cnt<30>
Mcount_cnt_cy<30>
Mcount_cnt_cy<31>
SLICE_X54Y28.CIN net (fanout=1) 0.000 Mcount_cnt_cy<31>
SLICE_X54Y28.COUT Tbyp 0.120 cnt<32>
Mcount_cnt_cy<32>
Mcount_cnt_cy<33>
SLICE_X54Y29.CIN net (fanout=1) 0.000 Mcount_cnt_cy<33>
SLICE_X54Y29.COUT Tbyp 0.120 cnt<34>
Mcount_cnt_cy<34>
Mcount_cnt_cy<35>
SLICE_X54Y30.CIN net (fanout=1) 0.000 Mcount_cnt_cy<35>
SLICE_X54Y30.CLK Tcinck 1.005 cnt<36>
Mcount_cnt_cy<36>
Mcount_cnt_xor<37>
cnt_37
------------------------------------------------- ---------------------------
Total 5.467ns (4.501ns logic, 0.966ns route)
(82.3% logic, 17.7% route)
--------------------------------------------------------------------------------
All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 5.725| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 1444 paths, 0 nets, and 134 connections
Design statistics:
Minimum period: 5.725ns{1} (Maximum frequency: 174.672MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Tue Dec 12 08:56:38 2006
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 99 MB
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