📄 run1.twr
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Release 9.1i Trace
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
D:\Xilinx91i\bin\nt\trce.exe -v 10 D:/ise_book/Example-4-1/xplorer/run1.ncd -o
D:/ise_book/Example-4-1/xplorer/run1.twr
D:/ise_book/Example-4-1/xplorer/run1.pcf
Design file: run1.ncd
Physical constraint file: run1.pcf
Device,package,speed: xc3s400,pq208,-4 (PRODUCTION 1.39 2006-10-19)
Report level: verbose report, limited to 10 items per constraint
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 7.321 ns HIGH 50%;
1444 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 5.725ns.
--------------------------------------------------------------------------------
Slack: 1.596ns (requirement - (data path - clock path skew + uncertainty))
Source: cnt_3 (FF)
Destination: cnt_37 (FF)
Requirement: 7.321ns
Data Path Delay: 5.707ns (Levels of Logic = 18)
Clock Path Skew: -0.018ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 7.321ns
Clock Uncertainty: 0.000ns
Maximum Data Path: cnt_3 to cnt_37
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X54Y13.YQ Tcko 0.720 cnt<2>
cnt_3
SLICE_X54Y13.G1 net (fanout=1) 0.966 cnt<3>
SLICE_X54Y13.COUT Topcyg 1.096 cnt<2>
Mcount_cnt_lut<3>
Mcount_cnt_cy<3>
SLICE_X54Y14.CIN net (fanout=1) 0.000 Mcount_cnt_cy<3>
SLICE_X54Y14.COUT Tbyp 0.120 cnt<4>
Mcount_cnt_cy<4>
Mcount_cnt_cy<5>
SLICE_X54Y15.CIN net (fanout=1) 0.000 Mcount_cnt_cy<5>
SLICE_X54Y15.COUT Tbyp 0.120 cnt<6>
Mcount_cnt_cy<6>
Mcount_cnt_cy<7>
SLICE_X54Y16.CIN net (fanout=1) 0.000 Mcount_cnt_cy<7>
SLICE_X54Y16.COUT Tbyp 0.120 cnt<8>
Mcount_cnt_cy<8>
Mcount_cnt_cy<9>
SLICE_X54Y17.CIN net (fanout=1) 0.000 Mcount_cnt_cy<9>
SLICE_X54Y17.COUT Tbyp 0.120 cnt<10>
Mcount_cnt_cy<10>
Mcount_cnt_cy<11>
SLICE_X54Y18.CIN net (fanout=1) 0.000 Mcount_cnt_cy<11>
SLICE_X54Y18.COUT Tbyp 0.120 cnt<12>
Mcount_cnt_cy<12>
Mcount_cnt_cy<13>
SLICE_X54Y19.CIN net (fanout=1) 0.000 Mcount_cnt_cy<13>
SLICE_X54Y19.COUT Tbyp 0.120 cnt<14>
Mcount_cnt_cy<14>
Mcount_cnt_cy<15>
SLICE_X54Y20.CIN net (fanout=1) 0.000 Mcount_cnt_cy<15>
SLICE_X54Y20.COUT Tbyp 0.120 cnt<16>
Mcount_cnt_cy<16>
Mcount_cnt_cy<17>
SLICE_X54Y21.CIN net (fanout=1) 0.000 Mcount_cnt_cy<17>
SLICE_X54Y21.COUT Tbyp 0.120 cnt<18>
Mcount_cnt_cy<18>
Mcount_cnt_cy<19>
SLICE_X54Y22.CIN net (fanout=1) 0.000 Mcount_cnt_cy<19>
SLICE_X54Y22.COUT Tbyp 0.120 cnt<20>
Mcount_cnt_cy<20>
Mcount_cnt_cy<21>
SLICE_X54Y23.CIN net (fanout=1) 0.000 Mcount_cnt_cy<21>
SLICE_X54Y23.COUT Tbyp 0.120 cnt<22>
Mcount_cnt_cy<22>
Mcount_cnt_cy<23>
SLICE_X54Y24.CIN net (fanout=1) 0.000 Mcount_cnt_cy<23>
SLICE_X54Y24.COUT Tbyp 0.120 cnt<24>
Mcount_cnt_cy<24>
Mcount_cnt_cy<25>
SLICE_X54Y25.CIN net (fanout=1) 0.000 Mcount_cnt_cy<25>
SLICE_X54Y25.COUT Tbyp 0.120 cnt<26>
Mcount_cnt_cy<26>
Mcount_cnt_cy<27>
SLICE_X54Y26.CIN net (fanout=1) 0.000 Mcount_cnt_cy<27>
SLICE_X54Y26.COUT Tbyp 0.120 cnt<28>
Mcount_cnt_cy<28>
Mcount_cnt_cy<29>
SLICE_X54Y27.CIN net (fanout=1) 0.000 Mcount_cnt_cy<29>
SLICE_X54Y27.COUT Tbyp 0.120 cnt<30>
Mcount_cnt_cy<30>
Mcount_cnt_cy<31>
SLICE_X54Y28.CIN net (fanout=1) 0.000 Mcount_cnt_cy<31>
SLICE_X54Y28.COUT Tbyp 0.120 cnt<32>
Mcount_cnt_cy<32>
Mcount_cnt_cy<33>
SLICE_X54Y29.CIN net (fanout=1) 0.000 Mcount_cnt_cy<33>
SLICE_X54Y29.COUT Tbyp 0.120 cnt<34>
Mcount_cnt_cy<34>
Mcount_cnt_cy<35>
SLICE_X54Y30.CIN net (fanout=1) 0.000 Mcount_cnt_cy<35>
SLICE_X54Y30.CLK Tcinck 1.005 cnt<36>
Mcount_cnt_cy<36>
Mcount_cnt_xor<37>
cnt_37
------------------------------------------------- ---------------------------
Total 5.707ns (4.741ns logic, 0.966ns route)
(83.1% logic, 16.9% route)
--------------------------------------------------------------------------------
Slack: 1.615ns (requirement - (data path - clock path skew + uncertainty))
Source: cnt_3 (FF)
Destination: cnt_36 (FF)
Requirement: 7.321ns
Data Path Delay: 5.688ns (Levels of Logic = 18)
Clock Path Skew: -0.018ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 7.321ns
Clock Uncertainty: 0.000ns
Maximum Data Path: cnt_3 to cnt_36
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X54Y13.YQ Tcko 0.720 cnt<2>
cnt_3
SLICE_X54Y13.G1 net (fanout=1) 0.966 cnt<3>
SLICE_X54Y13.COUT Topcyg 1.096 cnt<2>
Mcount_cnt_lut<3>
Mcount_cnt_cy<3>
SLICE_X54Y14.CIN net (fanout=1) 0.000 Mcount_cnt_cy<3>
SLICE_X54Y14.COUT Tbyp 0.120 cnt<4>
Mcount_cnt_cy<4>
Mcount_cnt_cy<5>
SLICE_X54Y15.CIN net (fanout=1) 0.000 Mcount_cnt_cy<5>
SLICE_X54Y15.COUT Tbyp 0.120 cnt<6>
Mcount_cnt_cy<6>
Mcount_cnt_cy<7>
SLICE_X54Y16.CIN net (fanout=1) 0.000 Mcount_cnt_cy<7>
SLICE_X54Y16.COUT Tbyp 0.120 cnt<8>
Mcount_cnt_cy<8>
Mcount_cnt_cy<9>
SLICE_X54Y17.CIN net (fanout=1) 0.000 Mcount_cnt_cy<9>
SLICE_X54Y17.COUT Tbyp 0.120 cnt<10>
Mcount_cnt_cy<10>
Mcount_cnt_cy<11>
SLICE_X54Y18.CIN net (fanout=1) 0.000 Mcount_cnt_cy<11>
SLICE_X54Y18.COUT Tbyp 0.120 cnt<12>
Mcount_cnt_cy<12>
Mcount_cnt_cy<13>
SLICE_X54Y19.CIN net (fanout=1) 0.000 Mcount_cnt_cy<13>
SLICE_X54Y19.COUT Tbyp 0.120 cnt<14>
Mcount_cnt_cy<14>
Mcount_cnt_cy<15>
SLICE_X54Y20.CIN net (fanout=1) 0.000 Mcount_cnt_cy<15>
SLICE_X54Y20.COUT Tbyp 0.120 cnt<16>
Mcount_cnt_cy<16>
Mcount_cnt_cy<17>
SLICE_X54Y21.CIN net (fanout=1) 0.000 Mcount_cnt_cy<17>
SLICE_X54Y21.COUT Tbyp 0.120 cnt<18>
Mcount_cnt_cy<18>
Mcount_cnt_cy<19>
SLICE_X54Y22.CIN net (fanout=1) 0.000 Mcount_cnt_cy<19>
SLICE_X54Y22.COUT Tbyp 0.120 cnt<20>
Mcount_cnt_cy<20>
Mcount_cnt_cy<21>
SLICE_X54Y23.CIN net (fanout=1) 0.000 Mcount_cnt_cy<21>
SLICE_X54Y23.COUT Tbyp 0.120 cnt<22>
Mcount_cnt_cy<22>
Mcount_cnt_cy<23>
SLICE_X54Y24.CIN net (fanout=1) 0.000 Mcount_cnt_cy<23>
SLICE_X54Y24.COUT Tbyp 0.120 cnt<24>
Mcount_cnt_cy<24>
Mcount_cnt_cy<25>
SLICE_X54Y25.CIN net (fanout=1) 0.000 Mcount_cnt_cy<25>
SLICE_X54Y25.COUT Tbyp 0.120 cnt<26>
Mcount_cnt_cy<26>
Mcount_cnt_cy<27>
SLICE_X54Y26.CIN net (fanout=1) 0.000 Mcount_cnt_cy<27>
SLICE_X54Y26.COUT Tbyp 0.120 cnt<28>
Mcount_cnt_cy<28>
Mcount_cnt_cy<29>
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