run3_map.map

该源码为xilinx ise教程的附带光盘源码

Release 9.1i Map J.30
Xilinx Map Application Log File for Design 'counter'

Design Information
------------------
Command Line   : D:\Xilinx91i\bin\nt\map.exe -p xc3s400-4pq208 -timing -ol high
-xe n -register_duplication -logic_opt on
D:/ise_book/Example-4-1/xplorer/counter.ngd -o
D:/ise_book/Example-4-1/xplorer/run3_map.ncd
D:/ise_book/Example-4-1/xplorer/run3.pcf 
Target Device  : xc3s400
Target Package : pq208
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.36 $
Mapped Date    : Tue Dec 12 08:57:14 2006

Mapping design into LUTs...
Writing file D:/ise_book/Example-4-1/xplorer/run3_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:9896be) REAL time: 0 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.2
.
Phase 4.2 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.4
.
Phase 7.4 (Checksum:42c1d79) REAL time: 3 secs 

Phase 8.28
Phase 8.28 (Checksum:4c4b3f8) REAL time: 3 secs 

Phase 9.8
.
...............
...............
Phase 9.8 (Checksum:99aad3) REAL time: 3 secs 

Phase 10.29
Phase 10.29 (Checksum:5f5e0f6) REAL time: 3 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 3 secs 

Phase 12.18
Phase 12.18 (Checksum:7270df4) REAL time: 4 secs 

Phase 13.5
Phase 13.5 (Checksum:7bfa473) REAL time: 4 secs 

REAL time consumed by placer: 4 secs 
CPU  time consumed by placer: 4 secs 
Invoking physical synthesis ...

Physical synthesis completed.
Inspecting route info ...
Route info done.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:          38 out of   7,168    1%
  Number of 4 input LUTs:              38 out of   7,168    1%
Logic Distribution:
  Number of occupied Slices:                           19 out of   3,584    1%
    Number of Slices containing only related logic:      19 out of      19  100%
    Number of Slices containing unrelated logic:          0 out of      19    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:          38 out of   7,168    1%
  Number of bonded IOBs:               19 out of     141   13%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  760
Additional JTAG gate count for IOBs:  912
Peak Memory Usage:  166 MB
Total REAL time to MAP completion:  13 secs 
Total CPU time to MAP completion:   12 secs 

Mapping completed.
See MAP report file "D:/ise_book/Example-4-1/xplorer/run3_map.mrp" for details.