📄 run4.twr
字号:
cnt_36
------------------------------------------------- ---------------------------
Total 5.543ns (4.710ns logic, 0.833ns route)
(85.0% logic, 15.0% route)
--------------------------------------------------------------------------------
Slack: -0.090ns (requirement - (data path - clock path skew + uncertainty))
Source: cnt_3 (FF)
Destination: cnt_35 (FF)
Requirement: 5.452ns
Data Path Delay: 5.542ns (Levels of Logic = 17)
Clock Path Skew: 0.000ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 5.452ns
Clock Uncertainty: 0.000ns
Maximum Data Path: cnt_3 to cnt_35
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X28Y25.YQ Tcko 0.720 cnt<2>
cnt_3
SLICE_X28Y25.G1 net (fanout=1) 0.921 cnt<3>
SLICE_X28Y25.COUT Topcyg 1.096 cnt<2>
Mcount_cnt_lut<3>
Mcount_cnt_cy<3>
SLICE_X28Y26.CIN net (fanout=1) 0.000 Mcount_cnt_cy<3>
SLICE_X28Y26.COUT Tbyp 0.120 cnt<4>
Mcount_cnt_cy<4>
Mcount_cnt_cy<5>
SLICE_X28Y27.CIN net (fanout=1) 0.000 Mcount_cnt_cy<5>
SLICE_X28Y27.COUT Tbyp 0.120 cnt<6>
Mcount_cnt_cy<6>
Mcount_cnt_cy<7>
SLICE_X28Y28.CIN net (fanout=1) 0.000 Mcount_cnt_cy<7>
SLICE_X28Y28.COUT Tbyp 0.120 cnt<8>
Mcount_cnt_cy<8>
Mcount_cnt_cy<9>
SLICE_X28Y29.CIN net (fanout=1) 0.000 Mcount_cnt_cy<9>
SLICE_X28Y29.COUT Tbyp 0.120 cnt<10>
Mcount_cnt_cy<10>
Mcount_cnt_cy<11>
SLICE_X28Y30.CIN net (fanout=1) 0.000 Mcount_cnt_cy<11>
SLICE_X28Y30.COUT Tbyp 0.120 cnt<12>
Mcount_cnt_cy<12>
Mcount_cnt_cy<13>
SLICE_X28Y31.CIN net (fanout=1) 0.000 Mcount_cnt_cy<13>
SLICE_X28Y31.COUT Tbyp 0.120 cnt<14>
Mcount_cnt_cy<14>
Mcount_cnt_cy<15>
SLICE_X28Y32.CIN net (fanout=1) 0.000 Mcount_cnt_cy<15>
SLICE_X28Y32.COUT Tbyp 0.120 cnt<16>
Mcount_cnt_cy<16>
Mcount_cnt_cy<17>
SLICE_X28Y33.CIN net (fanout=1) 0.000 Mcount_cnt_cy<17>
SLICE_X28Y33.COUT Tbyp 0.120 cnt<18>
Mcount_cnt_cy<18>
Mcount_cnt_cy<19>
SLICE_X28Y34.CIN net (fanout=1) 0.000 Mcount_cnt_cy<19>
SLICE_X28Y34.COUT Tbyp 0.120 cnt<20>
Mcount_cnt_cy<20>
Mcount_cnt_cy<21>
SLICE_X28Y35.CIN net (fanout=1) 0.000 Mcount_cnt_cy<21>
SLICE_X28Y35.COUT Tbyp 0.120 cnt<22>
Mcount_cnt_cy<22>
Mcount_cnt_cy<23>
SLICE_X28Y36.CIN net (fanout=1) 0.000 Mcount_cnt_cy<23>
SLICE_X28Y36.COUT Tbyp 0.120 cnt<24>
Mcount_cnt_cy<24>
Mcount_cnt_cy<25>
SLICE_X28Y37.CIN net (fanout=1) 0.000 Mcount_cnt_cy<25>
SLICE_X28Y37.COUT Tbyp 0.120 cnt<26>
Mcount_cnt_cy<26>
Mcount_cnt_cy<27>
SLICE_X28Y38.CIN net (fanout=1) 0.000 Mcount_cnt_cy<27>
SLICE_X28Y38.COUT Tbyp 0.120 cnt<28>
Mcount_cnt_cy<28>
Mcount_cnt_cy<29>
SLICE_X28Y39.CIN net (fanout=1) 0.000 Mcount_cnt_cy<29>
SLICE_X28Y39.COUT Tbyp 0.120 cnt<30>
Mcount_cnt_cy<30>
Mcount_cnt_cy<31>
SLICE_X28Y40.CIN net (fanout=1) 0.000 Mcount_cnt_cy<31>
SLICE_X28Y40.COUT Tbyp 0.120 cnt<32>
Mcount_cnt_cy<32>
Mcount_cnt_cy<33>
SLICE_X28Y41.CIN net (fanout=1) 0.000 Mcount_cnt_cy<33>
SLICE_X28Y41.CLK Tcinck 1.005 cnt<34>
Mcount_cnt_cy<34>
Mcount_cnt_xor<35>
cnt_35
------------------------------------------------- ---------------------------
Total 5.542ns (4.621ns logic, 0.921ns route)
(83.4% logic, 16.6% route)
--------------------------------------------------------------------------------
Slack: -0.071ns (requirement - (data path - clock path skew + uncertainty))
Source: cnt_3 (FF)
Destination: cnt_34 (FF)
Requirement: 5.452ns
Data Path Delay: 5.523ns (Levels of Logic = 17)
Clock Path Skew: 0.000ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 5.452ns
Clock Uncertainty: 0.000ns
Maximum Data Path: cnt_3 to cnt_34
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X28Y25.YQ Tcko 0.720 cnt<2>
cnt_3
SLICE_X28Y25.G1 net (fanout=1) 0.921 cnt<3>
SLICE_X28Y25.COUT Topcyg 1.096 cnt<2>
Mcount_cnt_lut<3>
Mcount_cnt_cy<3>
SLICE_X28Y26.CIN net (fanout=1) 0.000 Mcount_cnt_cy<3>
SLICE_X28Y26.COUT Tbyp 0.120 cnt<4>
Mcount_cnt_cy<4>
Mcount_cnt_cy<5>
SLICE_X28Y27.CIN net (fanout=1) 0.000 Mcount_cnt_cy<5>
SLICE_X28Y27.COUT Tbyp 0.120 cnt<6>
Mcount_cnt_cy<6>
Mcount_cnt_cy<7>
SLICE_X28Y28.CIN net (fanout=1) 0.000 Mcount_cnt_cy<7>
SLICE_X28Y28.COUT Tbyp 0.120 cnt<8>
Mcount_cnt_cy<8>
Mcount_cnt_cy<9>
SLICE_X28Y29.CIN net (fanout=1) 0.000 Mcount_cnt_cy<9>
SLICE_X28Y29.COUT Tbyp 0.120 cnt<10>
Mcount_cnt_cy<10>
Mcount_cnt_cy<11>
SLICE_X28Y30.CIN net (fanout=1) 0.000 Mcount_cnt_cy<11>
SLICE_X28Y30.COUT Tbyp 0.120 cnt<12>
Mcount_cnt_cy<12>
Mcount_cnt_cy<13>
SLICE_X28Y31.CIN net (fanout=1) 0.000 Mcount_cnt_cy<13>
SLICE_X28Y31.COUT Tbyp 0.120 cnt<14>
Mcount_cnt_cy<14>
Mcount_cnt_cy<15>
SLICE_X28Y32.CIN net (fanout=1) 0.000 Mcount_cnt_cy<15>
SLICE_X28Y32.COUT Tbyp 0.120 cnt<16>
Mcount_cnt_cy<16>
Mcount_cnt_cy<17>
SLICE_X28Y33.CIN net (fanout=1) 0.000 Mcount_cnt_cy<17>
SLICE_X28Y33.COUT Tbyp 0.120 cnt<18>
Mcount_cnt_cy<18>
Mcount_cnt_cy<19>
SLICE_X28Y34.CIN net (fanout=1) 0.000 Mcount_cnt_cy<19>
SLICE_X28Y34.COUT Tbyp 0.120 cnt<20>
Mcount_cnt_cy<20>
Mcount_cnt_cy<21>
SLICE_X28Y35.CIN net (fanout=1) 0.000 Mcount_cnt_cy<21>
SLICE_X28Y35.COUT Tbyp 0.120 cnt<22>
Mcount_cnt_cy<22>
Mcount_cnt_cy<23>
SLICE_X28Y36.CIN net (fanout=1) 0.000 Mcount_cnt_cy<23>
SLICE_X28Y36.COUT Tbyp 0.120 cnt<24>
Mcount_cnt_cy<24>
Mcount_cnt_cy<25>
SLICE_X28Y37.CIN net (fanout=1) 0.000 Mcount_cnt_cy<25>
SLICE_X28Y37.COUT Tbyp 0.120 cnt<26>
Mcount_cnt_cy<26>
Mcount_cnt_cy<27>
SLICE_X28Y38.CIN net (fanout=1) 0.000 Mcount_cnt_cy<27>
SLICE_X28Y38.COUT Tbyp 0.120 cnt<28>
Mcount_cnt_cy<28>
Mcount_cnt_cy<29>
SLICE_X28Y39.CIN net (fanout=1) 0.000 Mcount_cnt_cy<29>
SLICE_X28Y39.COUT Tbyp 0.120 cnt<30>
Mcount_cnt_cy<30>
Mcount_cnt_cy<31>
SLICE_X28Y40.CIN net (fanout=1) 0.000 Mcount_cnt_cy<31>
SLICE_X28Y40.COUT Tbyp 0.120 cnt<32>
Mcount_cnt_cy<32>
Mcount_cnt_cy<33>
SLICE_X28Y41.CIN net (fanout=1) 0.000 Mcount_cnt_cy<33>
SLICE_X28Y41.CLK Tcinck 0.986 cnt<34>
Mcount_cnt_xor<34>
cnt_34
------------------------------------------------- ---------------------------
Total 5.523ns (4.602ns logic, 0.921ns route)
(83.3% logic, 16.7% route)
--------------------------------------------------------------------------------
Slack: -0.003ns (requirement - (data path - clock path skew + uncertainty))
Source: cnt_3 (FF)
Destination: cnt_37 (FF)
Requirement: 5.452ns
Data Path Delay: 5.455ns (Levels of Logic = 18)
Clock Path Skew: 0.000ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 5.452ns
Clock Uncertainty: 0.000ns
Maximum Data Path: cnt_3 to cnt_37
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X28Y25.YQ Tcko 0.720 cnt<2>
cnt_3
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