run1.par

该源码为xilinx ise教程的附带光盘源码

Release 9.1i par J.30
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

GAVIN::  Tue Dec 12 08:56:26 2006

par -w -ol high -xe n D:/ise_book/Example-4-1/xplorer/run1_map.ncd
D:/ise_book/Example-4-1/xplorer/run1.ncd
D:/ise_book/Example-4-1/xplorer/run1.pcf 


Constraints file: D:/ise_book/Example-4-1/xplorer/run1.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment D:\Xilinx91i.
   "counter" is an NCD, version 3.1, device xc3s400, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.39 2006-10-19".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                        1 out of 8      12%
   Number of External IOBs                  19 out of 141    13%
      Number of LOCed IOBs                   0 out of 19      0%

   Number of Slices                         19 out of 3584    1%
      Number of SLICEMs                      0 out of 1792    0%



Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 6 secs 
Finished initial Timing Analysis.  REAL time: 6 secs 

Starting Router

Phase 1: 151 unrouted;       REAL time: 6 secs 

Phase 2: 131 unrouted;       REAL time: 6 secs 

Phase 3: 20 unrouted;       REAL time: 6 secs 

Phase 4: 20 unrouted; (0)      REAL time: 6 secs 

Phase 5: 20 unrouted; (0)      REAL time: 6 secs 

Phase 6: 20 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 6 secs 

Phase 8: 0 unrouted; (0)      REAL time: 6 secs 


Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 6 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX0| No   |   19 |  0.020     |  1.034      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.959
   The MAXIMUM PIN DELAY IS:                               2.315
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.660

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          72          73           5           0           0           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 7.321 ns HI | SETUP   |     1.596ns|     5.725ns|       0|           0
  GH 50%                                    | HOLD    |     1.456ns|            |       0|           0
------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  120 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file D:/ise_book/Example-4-1/xplorer/run1.ncd



PAR done!