run4.par

该源码为xilinx ise教程的附带光盘源码

Release 9.1i par J.30
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

GAVIN::  Tue Dec 12 08:57:59 2006

par -w -ol high -xe n D:/ise_book/Example-4-1/xplorer/run4_map.ncd
D:/ise_book/Example-4-1/xplorer/run4.ncd
D:/ise_book/Example-4-1/xplorer/run4.pcf 


Constraints file: D:/ise_book/Example-4-1/xplorer/run4.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment D:\Xilinx91i.
   "counter" is an NCD, version 3.1, device xc3s400, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.39 2006-10-19".


Device Utilization Summary:

   Number of BUFGMUXs                        1 out of 8      12%
   Number of External IOBs                  19 out of 141    13%
      Number of LOCed IOBs                   0 out of 19      0%

   Number of Slices                         19 out of 3584    1%
      Number of SLICEMs                      0 out of 1792    0%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 
Extra effort level (-xe):     Normal 

Starting initial Timing Analysis.  REAL time: 3 secs 
Finished initial Timing Analysis.  REAL time: 3 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896be) REAL time: 4 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 4 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.2
.
Phase 4.2 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 4 secs 

Phase 7.8
.
.
.
Phase 7.8 (Checksum:99afdd) REAL time: 7 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 7 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 7 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 7 secs 

REAL time consumed by placer: 8 secs 
CPU  time consumed by placer: 6 secs 
Writing design to file D:/ise_book/Example-4-1/xplorer/run4.ncd


Total REAL time to Placer completion: 8 secs 
Total CPU time to Placer completion: 6 secs 

Starting Router

Phase 1: 151 unrouted;       REAL time: 8 secs 

Phase 2: 131 unrouted;       REAL time: 8 secs 

Phase 3: 45 unrouted;       REAL time: 8 secs 

Phase 4: 45 unrouted; (18)      REAL time: 8 secs 

Phase 5: 45 unrouted; (18)      REAL time: 8 secs 

Phase 6: 45 unrouted; (18)      REAL time: 8 secs 

Phase 7: 0 unrouted; (642)      REAL time: 8 secs 

Phase 8: 0 unrouted; (642)      REAL time: 8 secs 

Updating file: D:/ise_book/Example-4-1/xplorer/run4.ncd with current fully routed design.

Phase 9: 0 unrouted; (606)      REAL time: 10 secs 

Phase 10: 0 unrouted; (602)      REAL time: 12 secs 

Phase 11: 0 unrouted; (562)      REAL time: 12 secs 

Phase 12: 0 unrouted; (562)      REAL time: 13 secs 

Phase 13: 0 unrouted; (562)      REAL time: 14 secs 

Updating file: D:/ise_book/Example-4-1/xplorer/run4.ncd with current fully routed design.

Phase 14: 0 unrouted; (562)      REAL time: 15 secs 

Phase 15: 0 unrouted; (562)      REAL time: 19 secs 

Phase 16: 0 unrouted; (562)      REAL time: 19 secs 

Phase 17: 0 unrouted; (562)      REAL time: 19 secs 

WARNING:Route:447 - CLK Net:clk_BUFGP may have excessive skew because 
   19 CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 19 secs 
Total CPU time to Router completion: 17 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX3| No   |   19 |  0.001     |  1.015      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.822
   The MAXIMUM PIN DELAY IS:                               4.433
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.437

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          57          21          36          35           1           0

Timing Score: 562

WARNING:Par:62 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in
   your design.

      Review the timing report using Timing Analyzer (In ISE select "Post-Place &
      Route Static Timing Report").  Go to the failing constraint(s) and select
      the "Timing Improvement Wizard" link for suggestions to correct each problem.

   Rerun Map with "-timing" (ISE process "Perform Timing -Driven
   Packing and Placement"

   Run Multi-Pass Place and Route in PAR using at least 5 "PAR Iterations"
   (ISE process "Multi Pass Place & Route").

   Use the Xilinx "xplorer" script to try special combinations of
   options known to produce very good results.
   See http://www.xilinx.com/ise/implementation/Xplorer.htm for details.

   Visit the Xilinx technical support web at http://support.xilinx.com and go to
   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
   in your design.

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
* TS_clk = PERIOD TIMEGRP "clk" 5.45238095  | SETUP   |    -0.210ns|     5.662ns|       4|         562
  ns HIGH 50%                               | HOLD    |     1.463ns|            |       0|           0
------------------------------------------------------------------------------------------------------


1 constraint not met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 20 secs 
Total CPU time to PAR completion: 18 secs 

Peak Memory Usage:  136 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - 4 errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 0

Writing design to file D:/ise_book/Example-4-1/xplorer/run4.ncd



PAR done!