counter.syr

该源码为xilinx ise教程的附带光盘源码

# FlipFlops/Latches                : 38
#      FDR                         : 38
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 18
#      IBUF                        : 2
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      21  out of   3584     0%  
 Number of Slice Flip Flops:            38  out of   7168     0%  
 Number of 4 input LUTs:                40  out of   7168     0%  
 Number of IOs:                         19
 Number of bonded IOBs:                 19  out of    141    13%  
 Number of GCLKs:                        1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 38    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.178ns (Maximum Frequency: 161.865MHz)
   Minimum input arrival time before clock: 7.541ns
   Maximum output required time after clock: 7.241ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 6.178ns (frequency: 161.865MHz)
  Total number of paths / destination ports: 1444 / 38
-------------------------------------------------------------------------
Delay:               6.178ns (Levels of Logic = 39)
  Source:            cnt_0 (FF)
  Destination:       cnt_37 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_0 to cnt_37
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.720   0.996  cnt_0 (cnt_0)
     LUT2:I1->O            1   0.551   0.000  Mcount_cnt_lut<0> (N6)
     MUXCY:S->O            1   0.500   0.000  Mcount_cnt_cy<0> (Mcount_cnt_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<1> (Mcount_cnt_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<2> (Mcount_cnt_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<3> (Mcount_cnt_cy<3>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<4> (Mcount_cnt_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<5> (Mcount_cnt_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<6> (Mcount_cnt_cy<6>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<7> (Mcount_cnt_cy<7>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<8> (Mcount_cnt_cy<8>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<9> (Mcount_cnt_cy<9>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<10> (Mcount_cnt_cy<10>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<11> (Mcount_cnt_cy<11>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<12> (Mcount_cnt_cy<12>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<13> (Mcount_cnt_cy<13>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<14> (Mcount_cnt_cy<14>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<15> (Mcount_cnt_cy<15>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<16> (Mcount_cnt_cy<16>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<17> (Mcount_cnt_cy<17>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<18> (Mcount_cnt_cy<18>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<19> (Mcount_cnt_cy<19>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<20> (Mcount_cnt_cy<20>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<21> (Mcount_cnt_cy<21>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<22> (Mcount_cnt_cy<22>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<23> (Mcount_cnt_cy<23>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<24> (Mcount_cnt_cy<24>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<25> (Mcount_cnt_cy<25>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<26> (Mcount_cnt_cy<26>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<27> (Mcount_cnt_cy<27>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<28> (Mcount_cnt_cy<28>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<29> (Mcount_cnt_cy<29>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<30> (Mcount_cnt_cy<30>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<31> (Mcount_cnt_cy<31>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<32> (Mcount_cnt_cy<32>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<33> (Mcount_cnt_cy<33>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<34> (Mcount_cnt_cy<34>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<35> (Mcount_cnt_cy<35>)
     MUXCY:CI->O           0   0.064   0.000  Mcount_cnt_cy<36> (Mcount_cnt_cy<36>)
     XORCY:CI->O           1   0.904   0.000  Mcount_cnt_xor<37> (Result<37>)
     FDR:D                     0.203          cnt_37
    ----------------------------------------
    Total                      6.178ns (5.182ns logic, 0.996ns route)
                                       (83.9% logic, 16.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 817 / 76
-------------------------------------------------------------------------
Offset:              7.541ns (Levels of Logic = 40)
  Source:            direction (PAD)
  Destination:       cnt_37 (FF)
  Destination Clock: clk rising

  Data Path: direction to cnt_37
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            39   0.821   1.893  direction_IBUF (direction_IBUF)
     INV:I->O              1   0.551   0.801  direction1_INV_0 (N5)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<0> (Mcount_cnt_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<1> (Mcount_cnt_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<2> (Mcount_cnt_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<3> (Mcount_cnt_cy<3>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<4> (Mcount_cnt_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<5> (Mcount_cnt_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<6> (Mcount_cnt_cy<6>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<7> (Mcount_cnt_cy<7>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<8> (Mcount_cnt_cy<8>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<9> (Mcount_cnt_cy<9>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<10> (Mcount_cnt_cy<10>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<11> (Mcount_cnt_cy<11>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<12> (Mcount_cnt_cy<12>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<13> (Mcount_cnt_cy<13>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<14> (Mcount_cnt_cy<14>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<15> (Mcount_cnt_cy<15>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<16> (Mcount_cnt_cy<16>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<17> (Mcount_cnt_cy<17>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<18> (Mcount_cnt_cy<18>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<19> (Mcount_cnt_cy<19>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<20> (Mcount_cnt_cy<20>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<21> (Mcount_cnt_cy<21>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<22> (Mcount_cnt_cy<22>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<23> (Mcount_cnt_cy<23>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<24> (Mcount_cnt_cy<24>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<25> (Mcount_cnt_cy<25>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<26> (Mcount_cnt_cy<26>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<27> (Mcount_cnt_cy<27>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<28> (Mcount_cnt_cy<28>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<29> (Mcount_cnt_cy<29>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<30> (Mcount_cnt_cy<30>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<31> (Mcount_cnt_cy<31>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<32> (Mcount_cnt_cy<32>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<33> (Mcount_cnt_cy<33>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<34> (Mcount_cnt_cy<34>)
     MUXCY:CI->O           1   0.064   0.000  Mcount_cnt_cy<35> (Mcount_cnt_cy<35>)
     MUXCY:CI->O           0   0.064   0.000  Mcount_cnt_cy<36> (Mcount_cnt_cy<36>)
     XORCY:CI->O           1   0.904   0.000  Mcount_cnt_xor<37> (Result<37>)
     FDR:D                     0.203          cnt_37
    ----------------------------------------
    Total                      7.541ns (4.847ns logic, 2.694ns route)
                                       (64.3% logic, 35.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              7.241ns (Levels of Logic = 1)
  Source:            cnt_37 (FF)
  Destination:       cnt_out<15> (PAD)
  Source Clock:      clk rising

  Data Path: cnt_37 to cnt_out<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   0.877  cnt_37 (cnt_37)
     OBUF:I->O                 5.644          cnt_out_15_OBUF (cnt_out<15>)
    ----------------------------------------
    Total                      7.241ns (6.364ns logic, 0.877ns route)
                                       (87.9% logic, 12.1% route)

=========================================================================
CPU : 11.09 / 13.05 s | Elapsed : 11.00 / 13.00 s
 
--> 

Total memory usage is 142808 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)