trf3761.c.bak

这个是基于ARM7的相关驱动代码

/*
*******************************************************************************
*                    Copyright (c) 2006, Comba Telecom System
*                             All Rights Reserved
*
* Purpose           : trf3761 drive File
* File Name         : trf3761.c

* Chip type         : LPC22XX(ARM7TDMI)
* IDE               : ADS1.2

* Revision history  :
    01a,2008/06/16,lihao  -- Creation(written)
  
* Description       :
* 用于GSM数字智能移频直放站的PLL器件3761的驱动。它完成的功能
* 1.3761的初始化，即完成3761的自校准过程。
* 2.3761的频点设置：经过自校准后只需要设置寄存器2和3 
    
*******************************************************************************
*/

#define _DEFINE_VAR_TRF3761_
#include "config.h"


/**************************************************************
* function name	: Trf3761Init(INT8U up_down)
* input			: up_down  0 for up and 1 for down, others null
* output		; 0 for no error and FF for error
***************************************************************/
void Trf3761Init(INT8U up_down)
{
	union
	{
	INT32U TwoWords;
	INT16U Words[2];
	}Trf3761ConfigTemp;

	#ifdef GSM_LOCATION   //近端机
		if (TRF3761_UP_LINK == up_down)
		{	
			Trf3761ConfigTemp.TwoWords = 0x102301A0 ; //register one X2
			FPGA_Reg(S_TRF3761_UP_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
			FPGA_Reg(S_TRF3761_UP_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
		}
		else if (TRF3761_DOWN_LINK == up_down)
		{
			Trf3761ConfigTemp.TwoWords = 0x102300A0 ; //register one X1
			FPGA_Reg(S_TRF3761_DN_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
			FPGA_Reg(S_TRF3761_DN_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
		}
		else
		{
			return  ;	
		}
	#else
		if (TRF3761_UP_LINK == up_down)
		{	
			Trf3761ConfigTemp.TwoWords = 0x102300A0 ; //register one X1
			FPGA_Reg(S_TRF3761_UP_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
			FPGA_Reg(S_TRF3761_UP_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
		}
		else if (TRF3761_DOWN_LINK == up_down)
		{
			Trf3761ConfigTemp.TwoWords = 0x102301A0 ; //register one X2
			FPGA_Reg(S_TRF3761_DN_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
			FPGA_Reg(S_TRF3761_DN_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
		}
		else
		{
			return ;	
		}
	#endif
/****************************************************************/
	Trf3761ConfigTemp.TwoWords = 0x9C2000E1 ; //register two for calibration
	
	if (TRF3761_UP_LINK == up_down)
	{
		FPGA_Reg(S_TRF3761_UP_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
		FPGA_Reg(S_TRF3761_UP_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
	}
	else if (TRF3761_DOWN_LINK == up_down)
	{
		FPGA_Reg(S_TRF3761_DN_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
		FPGA_Reg(S_TRF3761_DN_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
	}
	else
	{
		return  ;	
	}

}

/*********************************************************************
*function name	: Trf3761FreqSet(INT8U up_down, INT32U freq)
*input			: up_down 0 for up and 1 for down
*				: freq for 3761 output frequency(MHz)
*description	: 预分频因子为16  鉴相步进25K
**********************************************************************/
INT8U Trf3761FreqSet(INT8U up_down, INT32U freq)
{
	INT32U 	A_reg;
	INT32U	B_reg;
	
	union
	{
	INT32U TwoWords;
	INT16U Words[2];
	}Trf3761ConfigTemp;
	
	A_reg = (freq*40)%16;
	B_reg = (freq*40)/16 ;
	
	Trf3761ConfigTemp.TwoWords = ((freq << 18)&(0x7FFFFFFF))|0x0E1 ;
	
	if (TRF3761_UP_LINK == up_down)
	{
		FPGA_Reg(S_TRF3761_UP_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
		FPGA_Reg(S_TRF3761_UP_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
	}
	else if (TRF3761_DOWN_LINK == up_down)
	{
		FPGA_Reg(S_TRF3761_DN_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
		FPGA_Reg(S_TRF3761_DN_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
	}
	else
	{
		return 0xFF ;	
	}
/*********************************************************************/	
	Trf3761ConfigTemp.TwoWords = (A_reg<<6)|(B_reg<<13)|(0x22000012) ;
	
	if (TRF3761_UP_LINK == up_down)
	{
		FPGA_Reg(S_TRF3761_UP_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
		FPGA_Reg(S_TRF3761_UP_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
	}
	else if (TRF3761_DOWN_LINK == up_down)
	{
		FPGA_Reg(S_TRF3761_DN_Config_High_addr)= Trf3761ConfigTemp.Words[1] ;
		FPGA_Reg(S_TRF3761_DN_Config_Low_addr) = Trf3761ConfigTemp.Words[0] ;
	}
	else
	{
		return 0xFF ;	
	}
	
	return 0;	
}