📄 spmc75f2313a.h
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/* bit 6:0 :Reserve */
/* bit 7 :ASPEN, Auto Sampling mode enable */
/* bit 8 :ADCEXTRG, external ADC conversion request trigger from PB8 pad */
/* bit 10:9 :ADCFS, A/D converter clock selection */
/* =00: CPUCLK /8 */
/* =01: CPUCLK /16 */
/* =10: CPUCLK /32 */
/* =11: CPUCLK /64 */
/* bit 11 :Reserve */
/* bit 12 :VRXEN, AD Top voltage Source Selection */
/* bit 13 :Reserve */
/* bit 14 :ADCEN, ADC converter enable */
/* bit 15 :ADCCS, ADC converter chip select. (ADC Power on) */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 Reserved1 : 7;
UInt16 ASPEN : 1;
UInt16 ADCEXTRG : 1;
UInt16 ADCFS : 2;
UInt16 Reserved2 : 1;
UInt16 VRXEN : 1;
UInt16 Reserved3 : 1;
UInt16 ADCEN : 1;
UInt16 ADCCS : 1;
} B;
} P_ADC_Setup_DEF;
/*****************************************************************************/
/* ADC control register (P_ADC_Ctrl) */
/* bit 2:0 :ADCCHS, Select ADC converter channel input */
/* =010: ADC Channel 2 (PA2) */
/* =011: ADC Channel 3 (PA3) */
/* =100: ADC Channel 4 (PA4) */
/* =101: ADC Channel 5 (PA5) */
/* =110: ADC Channel 6 (PA6) */
/* =111: ADC Channel 7 (PA7) */
/* bit 5:3 :Reserve */
/* bit 6 :ADCSTR, Manual Start ADC Conversion */
/* bit 7 :ADCRDY, ADC conversion ready */
/* bit 13: 8 :Reserved */
/* bit 14 :ADCIE, ADC interrupt enable */
/* bit 15 :ADCIF, ADC interrupt flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 ADCCHS : 3;
UInt16 Reserved1 : 3;
UInt16 ADCSTR : 1;
UInt16 ADCRDY : 1;
UInt16 Reserved2 : 6;
UInt16 ADCIE : 1;
UInt16 ADCIF : 1;
} B;
} P_ADC_Ctrl_DEF;
/*****************************************************************************/
/* ADC Input Channels Select (P_ADC_Channel) */
/* bit 0 :ADCCH0, ADC Input Channel0 Enable */
/* bit 1 :ADCCH1, ADC Input Channel1 Enable */
/* bit 2 :ADCCH2, ADC Input Channel2 Enable */
/* bit 3 :ADCCH3, ADC Input Channel3 Enable */
/* bit 4 :ADCCH4, ADC Input Channel4 Enable */
/* bit 5 :ADCCH5, ADC Input Channel5 Enable */
/* bit 6 :ADCCH6, ADC Input Channel6 Enable */
/* bit 7 :ADCCH7, ADC Input Channel7 Enable */
/* bit 8:15 :Reserve */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 ADCCH0 : 1;
UInt16 ADCCH1 : 1;
UInt16 ADCCH2 : 1;
UInt16 ADCCH3 : 1;
UInt16 ADCCH4 : 1;
UInt16 ADCCH5 : 1;
UInt16 ADCCH6 : 1;
UInt16 ADCCH7 : 1;
UInt16 reserved : 8;
} B;
} P_ADC_Channel_DEF;
/*****************************************************************************/
/* ADC Data Register (P_ADC_Data) */
/* bit 5 - 0 : reserved */
/* bit 15 - 6 : ADCData, ADC conversion data */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved : 6;
UInt16 ADCData : 10;
} B;
} P_ADC_Data_DEF;
/*****************************************************************************/
/*****************************************************************************/
/* H. Standard Peripheral Interface, SPI register */
/*****************************************************************************/
/*****************************************************************************/
/* SPI control register (P_SPI_Ctrl) */
/* bit 2:0 :SPIFS, Master mode clock frequency selection */
/* bit 3 :SPISMPS, SPI sample mode selection for master mode */
/* bit 4 :SPIPOL, SPI clock polarity. SPI clock polarity select */
/* bit 5 :SPIPHA, SPI clock phase */
/* bit 7:6 :Reserve */
/* bit 8 :SPIMS, SPI mode selection */
/* bit 10:9 :SPISPCLK, Sampling clock select bits */
/* bit 11 :SPIRST, Write 1 to reset */
/* bit 14:12:Reserve */
/* bit 15 :SPIE, SPI enable */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SPIFS : 3;
UInt16 SPISMPS : 1;
UInt16 SPIPOL : 1;
UInt16 SPIPHA : 1;
UInt16 Reserved1 : 2;
UInt16 SPIMS : 1;
UInt16 SPISPCLK : 2;
UInt16 SPIRST : 1;
UInt16 Reserved2 : 3;
UInt16 SPIE : 1;
} B;
} P_SPI_Ctrl_DEF;
/*****************************************************************************/
/* SPI Tx status register (P_SPI_TxStatus) */
/* bit 12:0 :Reserve */
/* bit 13 :SPITXBF, SPI Transmission buffer full flag. */
/* bit 14 :SPITXIE, SPI Transmit interrupt enable */
/* bit 15 :SPITXIF, SPI Transmit interrupt flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 Reserved : 13;
UInt16 SPITXBF : 1;
UInt16 SPITXIE : 1;
UInt16 SPITXIF : 1;
} B;
} P_SPI_TxStatus_DEF;
/*****************************************************************************/
/* SPI Transmission Buffer (P_SPI_TxBuf) */
/* bit 7 - 0 : SPITXBUF,Write data sends to SDO pin */
/* bit 15- 8 : Reserve */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SPITXBUF : 8;
UInt16 reserved : 8;
} B;
} P_SPI_TxBuf_DEF;
/*****************************************************************************/
/* SPI Rx status register (P_SPI_RxStatus) */
/* bit 9:0 :Reserve */
/* bit 10 :FERR, Buffer full and overwrite */
/* bit 13:11:Reserve */
/* bit 14 :SPIRXIE, SPI receive interrupt enable */
/* bit 15 :SPIRXIF, SPI receive interrupt flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 Reserved1 : 10;
UInt16 FERR : 1;
UInt16 Reserved2 : 3;
UInt16 SPIRXIE : 1;
UInt16 SPIRXIF : 1;
} B;
} P_SPI_RxStatus_DEF;
/*****************************************************************************/
/* SPI Receive Buffer (P_SPI_RxBuf) */
/* bit 7 - 0 : SPIRXBUF,Read data from SDI pin */
/* bit 15- 8 : Reserve */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SPIRXBUF : 8;
UInt16 reserved : 8;
} B;
} P_SPI_RxBuf_DEF;
/*****************************************************************************/
/* Reset status register (P_Reset_Status) */
/* bit 0 : EXTRF, External reset pin reset flag */
/* bit 1 : PORF, Power-on reset flag */
/* bit 2 : WDRF, Watchdog reset flag */
/* bit 3 : LVRF, Low voltage reset flag */
/* bit 4 : reserved */
/* bit 5 : IARF, Illegal address reset flag */
/* bit 6 : IIRF, Illegal instruction reset flag */
/* bit 7 - 8 : reserved */
/* bit 9 - 15 : FCHK, Flag clear check bits pattern */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 EXTRF : 1;
UInt16 PORF : 1;
UInt16 WDRF : 1;
UInt16 LVRF : 1;
UInt16 reserved1 : 1;
UInt16 IARF : 1;
UInt16 IIRF : 1;
UInt16 reserved2 : 2;
UInt16 FCHK : 7;
} B;
} P_Reset_Status_DEF;
/*****************************************************************************/
/* System Clock control register (P_Clk_Ctrl) */
/* bit 13 - 0 : reserved */
/* bit 14 : OSCIE, Oscillator fail interrupt enable bit */
/* bit 15 : OSCSF, Oscillator status flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved : 14;
UInt16 OSCIE : 1;
UInt16 OSCSF : 1;
} B;
} P_Clk_Ctrl_DEF;
/*****************************************************************************/
/* System Option Register (P_System_Option) */
/* bit 0 : CLK Source, Clock Source Selection */
/* bit 1 : WDG, enable watchdog function */
/* bit 2 : LVR, enable low voltage reset function */
/* bit 3 : LVD, enable low voltage detection function */
/* bit 4 : Security, security selection bit */
/* bit 5 - 15 : Verification Pattern, Writer will write 010 1010 1010(0x2AA) */
/* to this area */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 CLK : 1;
UInt16 WDG : 1;
UInt16 LVR : 1;
UInt16 LVD : 1;
UInt16 Security : 1;
UInt16 Verification : 11;
} B;
} P_System_Option_DEF;
/*****************************************************************************/
/* WatchDog Ctrl Register (P_WatchDog_Ctrl) */
/* bit 0 - 2 : WDPS, Watchdog Timer Time-out Selections */
/* bit 3 - 7 : WDCHK, Watchdog control register check bits */
/* bit 8 - 13 : reserved */
/* bit 14 : WDRS, Watchdog reset select bit */
/* bit 15 : WDEN, Watchdog timer enable bit */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 WDPS : 3;
UInt16 WDCHK : 5;
UInt16 reserved : 6;
UInt16 WDRS : 1;
UInt16 WDEN : 1;
} B;
} P_WatchDog_Ctrl_DEF;
/*****************************************************************************/
/* The watchdog clearance port (P_WatchDog_Clr) */
/* bit 0 - 15 : WDTCLR, Write 0xA005 to clear watchdog timer */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 WDTCLR : 16;
} B;
} P_WatchDog_Clr_DEF;
/*****************************************************************************/
/* Wake-up Control Register (P_Wakeup_Ctrl) */
/* bit 0 - 3 : Reserve */
/* bit 4 : CMTWE, Compare match timer wake-up enable bit */
/* bit 5 : PDC0WE, PDC channel 0 wake-up enable bit */
/* bit 6 : PDC1WE, PDC channel 1 wake-up enable bit */
/* bit 7 : TPM2WE, TPM channel 2 wake-up enable bit */
/* bit 8 - 10 : reserved */
/* bit 11 : EXT0WE, External interrupt 0 wake-up enable bit */
/* bit 12 : EXT1WE, External interrupt 1 wake-up enable bit */
/* bit 13 : SPIWE, SPI wake-up enable bit */
/* bit 14 : UARTWE, UART wake-up enable bit */
/* bit 15 : KEYWE, Key-change wake-up enable bit */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 Reserve1 : 4;
UInt16 CMTWE : 1;
UInt16 PDC0WE : 1;
UInt16 PDC1WE : 1;
UInt16 TPM2WE : 1;
UInt16 reserved2 : 3;
UInt16 EXT0WE : 1;
UInt16 EXT1WE : 1;
UInt16 SPIWE : 1;
UInt16 UARTWE : 1;
UInt16 KEYWE : 1;
} B;
} P_Wakeup_Ctrl_DEF;
/*****************************************************************************/
/* UART Data Register (P_UART_Data) */
/* bit 0 - 7 : UARTDATA, UART Data Read/Write Register */
/* bit 8 : FE, Frame Error (Ready-only) */
/* bit 9 : PE, Parity Error (Ready-only) */
/* bit 10 : reserved */
/* bit 11 : OE, Overrun Error (Ready-only) */
/* bit 12 - 15: reserved */
/*****************************************************************************/
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