📄 spmc75_regs.h
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UInt16 W;
struct
{
UInt16 SPIRXBUF : 8;
UInt16 reserved : 8;
} B;
} P_SPI_RxBuf_DEF;
/*****************************************************************************/
/* Reset status register (P_Reset_Status) */
/* bit 0 : EXTRF, External reset pin reset flag */
/* bit 1 : PORF, Power-on reset flag */
/* bit 2 : WDRF, Watchdog reset flag */
/* bit 3 : LVRF, Low voltage reset flag */
/* bit 4 : reserved */
/* bit 5 : IARF, Illegal address reset flag */
/* bit 6 : IIRF, Illegal instruction reset flag */
/* bit 7 - 8 : reserved */
/* bit 9 - 15 : FCHK, Flag clear check bits pattern */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 EXTRF : 1;
UInt16 PORF : 1;
UInt16 WDRF : 1;
UInt16 LVRF : 1;
UInt16 reserved1 : 1;
UInt16 IARF : 1;
UInt16 IIRF : 1;
UInt16 reserved2 : 2;
UInt16 FCHK : 7;
} B;
} P_Reset_Status_DEF;
/*****************************************************************************/
/* System Clock control register (P_Clk_Ctrl) */
/* bit 13 - 0 : reserved */
/* bit 14 : OSCIE, Oscillator fail interrupt enable bit */
/* bit 15 : OSCSF, Oscillator status flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved : 14;
UInt16 OSCIE : 1;
UInt16 OSCSF : 1;
} B;
} P_Clk_Ctrl_DEF;
/*****************************************************************************/
/* System Option Register (P_System_Option) */
/* bit 0 : CLK Source, Clock Source Selection */
/* bit 1 : WDG, enable watchdog function */
/* bit 2 : LVR, enable low voltage reset function */
/* bit 3 : LVD, enable low voltage detection function */
/* bit 4 : Security, security selection bit */
/* bit 5 - 15 : Verification Pattern, Writer will write 010 1010 1010(0x2AA) */
/* to this area */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 CLK : 1;
UInt16 WDG : 1;
UInt16 LVR : 1;
UInt16 LVD : 1;
UInt16 Security : 1;
UInt16 Verification : 11;
} B;
} P_System_Option_DEF;
/*****************************************************************************/
/* WatchDog Ctrl Register (P_WatchDog_Ctrl) */
/* bit 0 - 2 : WDPS, Watchdog Timer Time-out Selections */
/* bit 3 - 7 : WDCHK, Watchdog control register check bits */
/* bit 8 - 13 : reserved */
/* bit 14 : WDRS, Watchdog reset select bit */
/* bit 15 : WDEN, Watchdog timer enable bit */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 WDPS : 3;
UInt16 WDCHK : 5;
UInt16 reserved : 6;
UInt16 WDRS : 1;
UInt16 WDEN : 1;
} B;
} P_WatchDog_Ctrl_DEF;
/*****************************************************************************/
/* The watchdog clearance port (P_WatchDog_Clr) */
/* bit 0 - 15 : WDTCLR, Write 0xA005 to clear watchdog timer */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 WDTCLR : 16;
} B;
} P_WatchDog_Clr_DEF;
/*****************************************************************************/
/* Wake-up Control Register (P_Wakeup_Ctrl) */
/* bit 0 - 3 : Reserve */
/* bit 4 : CMTWE, Compare match timer wake-up enable bit */
/* bit 5 : PDC0WE, PDC channel 0 wake-up enable bit */
/* bit 6 : PDC1WE, PDC channel 1 wake-up enable bit */
/* bit 7 : TPM2WE, TPM channel 2 wake-up enable bit */
/* bit 8 - 10 : reserved */
/* bit 11 : EXT0WE, External interrupt 0 wake-up enable bit */
/* bit 12 : EXT1WE, External interrupt 1 wake-up enable bit */
/* bit 13 : SPIWE, SPI wake-up enable bit */
/* bit 14 : UARTWE, UART wake-up enable bit */
/* bit 15 : KEYWE, Key-change wake-up enable bit */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 Reserve1 : 4;
UInt16 CMTWE : 1;
UInt16 PDC0WE : 1;
UInt16 PDC1WE : 1;
UInt16 TPM2WE : 1;
UInt16 reserved2 : 3;
UInt16 EXT0WE : 1;
UInt16 EXT1WE : 1;
UInt16 SPIWE : 1;
UInt16 UARTWE : 1;
UInt16 KEYWE : 1;
} B;
} P_Wakeup_Ctrl_DEF;
/*****************************************************************************/
/* UART Data Register (P_UART_Data) */
/* bit 0 - 7 : UARTDATA, UART Data Read/Write Register */
/* bit 8 : FE, Frame Error (Ready-only) */
/* bit 9 : PE, Parity Error (Ready-only) */
/* bit 10 : reserved */
/* bit 11 : OE, Overrun Error (Ready-only) */
/* bit 12 - 15: reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 UARTDATA : 8;
UInt16 FE : 1;
UInt16 PE : 1;
UInt16 reserved1 : 1;
UInt16 OE : 1;
UInt16 reserved2 : 4;
} B;
} P_UART_Data_DEF;
/*****************************************************************************/
/* UART Reception Error Flag Register (P_UART_RXStatus) */
/* bit 0 : FE, Frame Error. */
/* bit 1 : PE, Parity Error. */
/* bit 2 : BE, Break Error. */
/* bit 3 : OE, Overrun Error. */
/* bit 4 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 FE : 1;
UInt16 PE : 1;
UInt16 reserve1 : 1;
UInt16 OE : 1;
UInt16 reserved2 : 12;
} B;
} P_UART_RXStatus_DEF;
/*****************************************************************************/
/* UART Control Register (P_UART_Ctrl) */
/* bit 0 : reserved */
/* bit 1 : PEN, Parity Enable */
/* bit 2 : PSEL, Parity Selection */
/* bit 3 : SBSEL, Stop Bit Size Selection */
/* bit 4 - 8 : reserved */
/* bit 9 : RXCHSEL,Reception data channel selection */
/* 0: UART reception from RXD2 */
/* 1: UART reception from RXD2 */
/* bit 10 : TXCHSEL, Transmission data channel selection */
/* 0: UART transmission to TXD2 */
/* 1. UART transmission to TXD1 */
/* bit 11 : Reset, Software reset */
/* bit 12 : TXEN, txd pin enable */
/* bit 13 : RXEN, rxd pin enable */
/* bit 14 : TXIE , Transmit Interrupt Enable */
/* bit 15 : RXIE , Receive Interrupt Enable */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved1 : 1;
UInt16 PEN : 1;
UInt16 PSEL : 1;
UInt16 SBSEL : 1;
UInt16 reserved2 : 5;
UInt16 RXCHSEL : 1;
UInt16 TXCHSEL : 1;
UInt16 Reset : 1;
UInt16 TXEN : 1;
UInt16 RXEN : 1;
UInt16 TXIE : 1;
UInt16 RXIE : 1;
} B;
} P_UART_Ctrl_DEF;
/*****************************************************************************/
/* UART Baud Rate Setup Register (P_UART_BaudRate) */
/* bit 0 - 15 : UARTBUD, UART Baud Rate Divisor */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 UARTBUD : 16;
} B;
} P_UART_BaudRate_DEF;
/*****************************************************************************/
/* UART Status Register (P_UART_Status) */
/* bit 0 - 2 : reserved */
/* bit 3 : BY, BUSY flag */
/* bit 4 - 5 : reserved */
/* bit 6 : RXFF, Receive FIFO Full Flag */
/* bit 7 - 13 : reserved */
/* bit 14 : TXIF, Transmit Interrupt Flag */
/* bit 15 : RXIF, Receive Interrupt Flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved1 : 3;
UInt16 BY : 1;
UInt16 reserved2 : 2;
UInt16 RXBF : 1;
UInt16 reserved3 : 7;
UInt16 TXIF : 1;
UInt16 RXIF : 1;
} B;
} P_UART_Status_DEF;
/*****************************************************************************/
/* Interrupt status Register (P_INT_Status) */
/* bit 0 : FTIF, Fault protection interrupt status flag */
/* bit 1 : OSCSF, Oscillator status flag */
/* bit 2 : OLIF, Overload interrupt status flag */
/* bit 3 : reserved */
/* bit 4 : CMTIF, Compare match timer interrupt status flag */
/* bit 5 : PDC0IF, Timer/PWM module channel 0 interrupt status flag */
/* bit 6 : PDC1IF, Timer/PWM module channel 1 interrupt status flag */
/* bit 7 : TPM2IF, Timer/PWM module channel 2 interrupt status flag */
/* bit 8 : MCP3IF, Timer/PWM module channel 3 interrupt status flag */
/* bit 9 : MCP4IF, Timer/PWM module channel 4 interrupt status flag */
/* bit 10 : ADCIF, A/D converter interrupt status flag */
/* bit 11 : EXT0IF, External interrupt 0 status flag */
/* bit 12 : EXT1IF, External interrupt 1 status flag */
/* bit 13 : SPIIF, SPI interrupt status flag */
/* bit 14 : UARTIF, UART interrupt status flag */
/* bit 15 : KEYIF, Key-change interrupt status flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 FTIF : 1;
UInt16 OSCSF : 1;
UInt16 OLIF : 1;
UInt16 reserved : 1;
UInt16 CMTIF : 1;
UInt16 PDC0IF : 1;
UInt16 PDC1IF : 1;
UInt16 TPM2IF : 1;
UInt16 MCP3IF : 1;
UInt16 MCP4IF : 1;
UInt16 ADCIF : 1;
UInt16 EXT0IF : 1;
UInt16 EXT1IF : 1;
UInt16 SPIIF : 1;
UInt16 UARTIF : 1;
UInt16 KEYIF : 1;
} B;
} P_INT_Status_DEF;
/*****************************************************************************/
/* IRQ and FIQ selection Register (P_INT_Priority) */
/* bit 0 : FTIP, Fault protection interrupt priority select bit */
/* bit 1 : OSCIP, Oscillator fail interrupt priority select bit */
/* bit 2 : OLIP, Overload interrupt priority select bit */
/* bit 3 : reserved */
/* bit 4 : CMTIP, CMT interrupt priority select bit */
/* bit 5 : PDC0IP, PDC ch. 0 interrupt priority select bit */
/* bit 6 : PDC1IP, PDC ch. 1 interrupt priority select bit */
/* bit 7 : TPM2IP, TPM ch. 2 interrupt priority select bit */
/* bit 8 : MCP3IP, MCP ch. 3 interrupt priority select bit */
/* bit 9 : MCP4IP, MCP ch. 4 interrupt priority select bit */
/* bit 10 : ADCIP, ADC interrupt priority select bit */
/* bit 11 : EXTIP, External interrupt priority select bit */
/* bit 12 : reserved */
/* bit 13 : SPIIP, SPI interrupt priority select bit */
/* bit 14 : UARTIP, UART interrupt priority select bit */
/* bit 15 : KEYIP, Key-change interrupt priority select bit */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 FTIP : 1;
UInt16 OSCIP : 1;
UInt16 OLIP : 1;
UInt16 reserved1 : 1;
UInt16 CMTIP : 1;
UInt16 PDC0IP : 1;
UInt16 PDC1IP : 1;
UInt16 TPM2IP : 1;
UInt16 MCP3IP : 1;
UInt16 MCP4IP : 1;
UInt16 ADCIP : 1;
UInt16 EXTIP : 1;
UInt16 reserved2 : 1;
UInt16 SPIIP : 1;
UInt16 UARTIP : 1;
UInt16 KEYIP : 1;
} B;
} P_INT_Priority_DEF;
/*****************************************************************************/
/* Miscellaneous Interrupt control register (P_MisINT_Ctrl) */
/* bit 0 - 10 : reserved */
/* bit 11 : EXT0IE, External interrupt 0 enable bit */
/* bit 12 : EXT1IE, External interrupt 1 enable bit */
/* bit 13 : EXT0MS, External interrupt 0 trigger mode selection */
/* bit 14 : EXT1MS, External interrupt 1 trigger mode selection */
/* bit 15 : KEYIE, Key-change interrupt enable bit */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved1 : 11;
UInt16 EXT0IE : 1;
UInt16 EXT1IE : 1;
UInt16 EXT0MS : 1;
UInt16 EXT1MS : 1;⌨️ 快捷键说明
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