emac2_regbits.h

实现在指定视频服务器下的视频点播

//
// EMAC2_setup.h (just the register bit defines)
//
// $Log: EMAC2_setup.h,v $
// Revision 1.73  2004-09-09 17:45:10-04  jskroch
//


// -----------------------------------------------------------------------
//                         REGISTER BITS				//
// -----------------------------------------------------------------------

// EMAC2_OPMODE 	0x00	MAC Operating Mode Register 
// --------------------------------------------------------------
// 					// Configuration Modes:
//			31,30,29	//      Reserved
#define EMAC2_DRO	(1<< 28 )	// (23) Disable Receive Own Frames
#define EMAC2_LB	(1<< 27 )	// (21) Internal Loopback Enable
#define EMAC2_HDX	(0<< 26 )	// (20) Half-Duplex Mode
#define EMAC2_FDX	(1<< 26 )	// (20) Full-Duplex Mode
#define EMAC2_RMII_10	(1<< 25 )	// (25) RMII 10-Mbit/s Rate Select
#define EMAC2_MII	(0<< 24 )	// (24) MII Mode  (bit 24 ==0)
#define EMAC2_RMII	(1<< 24 )	// (24) RMII Mode (bit 24 ==1)

// 					// Transmit Modes:
#define EMAC2_LCTRE	(1<< 23 )	// (12) Enable TX Retry on Late Collision
#define EMAC2_DRTY	(1<< 22 )	// (10) Disable TX Retry on Collision
#define EMAC2_BOLMT_10	( 0 <<20)	// ( 6) Back-Off-Limit = 10 bits
#define EMAC2_BOLMT_8 	( 1 <<20)	// ( 6) Back-Off-Limit =  8 bits
#define EMAC2_BOLMT_4 	( 2 <<20)	// ( 6) Back-Off-Limit =  4 bits
#define EMAC2_BOLMT_1 	( 3 <<20)	// ( 6) Back-Off-Limit =  1 bit
#define EMAC2_DC	(1<< 19 )	// ( 5) Deferral Check.
#define	EMAC2_DTXCRC	(1<< 18 )	// (28) Disable Automatic TX CRC Generation
#define	EMAC2_DTXPAD	(1<< 17 )	// (27) Disable Automatic TX Padding
#define EMAC2_TE	(1<< 16 )	// ( 3) Transmitter

// 					// Receive Modes:
//			   15-13   	//      Reserved
#define EMAC2_RA	(1<< 12 )	// (31) Receive-All
#define EMAC2_PSF	(1<< 11 )	//      Pass Short Frames
#define EMAC2_PBF	(1<< 10 )	// (16) Pass Bad Frames
#define EMAC2_DBF	(1<<  9 )	// (11) Discard Broadcast Frames
#define EMAC2_IF	(1<<  8 )	// (17) Inverse Filtering.

#define EMAC2_PR	(1<<  7 )	// (18) Promiscuous Mode.
#define EMAC2_PAM	(1<<  6 )	// (19) Pass-All-Multicast Mode
//					// 
#define EMAC2_HM	(1<<  5 )	// (13) Hash-Multicast Mode
#define EMAC2_HU	(1<<  4 )	// (13) Hash-Unicast Mode
//			     3,2     	//      Reserved
#define EMAC2_ASTP	(1<<  1 )	// ( 8) Automatic Pad Stripping
#define EMAC2_RE	(1<<  0 )	// ( 2) Receiver Enable


//  EMAC2_MACAL		0x04	MAC Address Low (32 LSBs) 
//  EMAC2_MACAH		0x08	MAC Address High (16 MSBs) 
// -------------------------------------------------------

//  EMAC2_MHASHL	0x0C	Multicast Hash Table Low (bins 31-0) 
//  EMAC2_MHASHH	0x10	Multicast Hash Table High (bins 63-32) 
// -------------------------------------------------------

//  EMAC2_STAA 		0x14	STA (Station Management) Address Register
// -------------------------------------------------------
#define	EMAC2_STABUSY	(1<< 0 )	// STA Busy Status.
#define	EMAC2_STAOP_RD	( 0<< 1 )	// Station Management Operation=Read
#define	EMAC2_STAOP_WR	( 1<< 1 )	// Station Management Operation=Write
#define	EMAC2_STADISPRE	( 1<< 2 )	// Disable Stn Mgt Frame Preamble
#define	EMAC2_STAIE	( 1<< 3 )	// Stn Mgt Frame-Done Interrupt Enable
#define	EMAC2_REGAD(n)	(((n)&0x1F)<<  6 )	// STA Register Address.
#define	EMAC2_PHYAD(n)	(((n)&0x1F)<< 11 )	// PHY Device Address

//  EMAC2_STAD		0x18 	STA Data Register 
// -------------------------------------------------------

//  EMAC2_FLC		0x1C	Flow Control Register
// -------------------------------------------------------
#define	EMAC2_FLCBUSY	(1<< 0 )	// Send Flow Control Frame / Flow Control Busy Status
#define	EMAC2_FLCE	(1<< 1 )	// Flow Control Enable
#define	EMAC2_PCF	(1<< 2 )	// Pass Control Frames
#define	EMAC2_BKPRSEN	(1<< 3 )	// Backpressure Enable
#define	EMAC2_FLCPAUSE(n) (((n)&0xFFFF)<< 16 )	// Pause Time

//  EMAC2_VLAN1 	0x20	VLAN1 Tag Register
//  EMAC2_VLAN2	  	0x24	VLAN2 Tag Register
// -------------------------------------------------------

//  EMAC2_TESTMODE 	0x28	Testmode Register (Resrved)
// -------------------------------------------------------
#define EMAC2_TEST_FAST	(1<< 15)	// Fast slot counter testmode
#define EMAC2_TEST_MMC	(1<< 14)	// MMC RAM Testmode
#define EMAC2_TEST_CLKREQ (1<< 13)	// Force clock tree enable testmode

//  EMAC2_WK_CSR	0x2C	Wake-up Control/Status Register
// -------------------------------------------------------
#define	EMAC2_CAPWKFRM	(1<<  0 )	// Capture Wake-Up Frames
#define	EMAC2_MPKE	(1<<  1 )	// Magic Packet Wake-up Enable
#define	EMAC2_RWKE	(1<<  2 )	// Remote Wake-Up Frame
#define	EMAC2_GUWKE	(1<<  4 )	// Global Unicast Wake Enable
#define	EMAC2_MPKS	(1<<  5 )	// Magic Packet Received Status
#define	EMAC2_RWKS0	(1<<  8 )	// Wake-up Frame 0 Received Status
#define	EMAC2_RWKS1	(1<<  9 )	// Wake-up Frame 1 Received Status
#define	EMAC2_RWKS2	(1<< 10 )	// Wake-up Frame 2 Received Status
#define	EMAC2_RWKS3	(1<< 11 )	// Wake-up Frame 3 Received Status


//  EMAC2_WK_CMD	x040	Filter Commands Register 
// -------------------------------------------------------
#define	EMAC2_WK_EN0	(1<< 0 )	// Wake-Up Filter 0 Enable
#define	EMAC2_WK_MCST0	(1<< 3 )	// Wake-Up Filter 0 Multicast/-Unicast Sel
#define	EMAC2_WK_EN1  	(1<< 8 )	// Wake-Up Filter 1 Enable
#define	EMAC2_WK_MCST1	(1<< 11 )	// Wake-Up Filter 1 Multicast/-Unicast Sel
#define	EMAC2_WK_EN2  	(1<< 16 )	// Wake-Up Filter 2 Enable
#define	EMAC2_WK_MCST2	(1<< 19 )	// Wake-Up Filter 2 Multicast/-Unicast Sel
#define	EMAC2_WK_EN3  	(1<< 24 )	// Wake-Up Filter 3 Enable
#define	EMAC2_WK_MCST3	(1<< 27 )	// Wake-Up Filter 3 Multicast/-Unicast Sel


//  EMAC2_WK_OFST	0x44	Filter Offsets Register 
// -------------------------------------------------------
#define	EMAC2_WK_OFST0(n) (((n)&0xFF)<<  0 ) // Wake-Up Filter 0 Byte Offset
#define	EMAC2_WK_OFST1(n) (((n)&0xFF)<<  8 ) // Wake-Up Filter 1 Byte Offset
#define	EMAC2_WK_OFST2(n) (((n)&0xFF)<< 16 ) // Wake-Up Filter 2 Byte Offset
#define	EMAC2_WK_OFST3(n) (((n)&0xFF)<< 24 ) // Wake-Up Filter 3 Byte Offset
#define	EMAC2_WK_OFFSETS(x0,x1,x2,x3)  \
	( EMAC2_WK_OFST0(x0) | EMAC2_WK_OFST1(x1)|EMAC2_WK_OFST2(x2) | EMAC2_WK_OFST3(x3) )

//  EMAC2_WK_CRC01	0x48	Filter 0,1 CRC-16 Register 
// -------------------------------------------------------
#define	EMAC2_WK_CRC0(n) (((n)&0xFFFF)<<   0 ) // Wake-Up Filter 0 Target CRC
#define	EMAC2_WK_CRC1(n) (((n)&0xFFFF)<<  16 ) // Wake-Up Filter 1 Target CRC


//  EMAC2_WK_CRC23	0x4C	Filter 2,3 CRC-16 Register
// -------------------------------------------------------
#define	EMAC2_WK_CRC2(n) (((n)&0xFFFF)<<   0 ) // Wake-Up Filter 2 Target CRC
#define	EMAC2_WK_CRC3(n) (((n)&0xFFFF)<<  16 ) // Wake-Up Filter 3 Target CRC


//  EMAC2_SYSCTL	0x60	EMAC System Control Register 
// -------------------------------------------------------
#define	EMAC2_PHYIE	(1<<  0 )	// PHY_INT Interrupt Enable
#define	EMAC2_RXDWA	(1<<  1 )	// Receive Frame DMA Word Alignment:
#define	EMAC2_RXCKS	(1<<  2 )	// Enable Receive Frame TCP/UDP Checksum Computation
#define	EMAC2_TXFIFG	(1<<  3 )	// Enable Transmit Fast IFG (lower start FIFO level)
#define	EMAC2_MDCDIV(n)	(((n)&0x3F)<<8 )	// SCLK:MDC Clock Divisor:


//  EMAC2_SYSSTAT	0x64 	EMAC System Status Register 
// -------------------------------------------------------
#define	EMAC2_PHYINT	(1<< 0 )	// PHY_INT Interrupt Status
#define	EMAC2_MMCINT	(1<< 1 )	// MMC Counter Interrupt Status
#define	EMAC2_RXFSINT	(1<< 2 )	// RX Frame-Status Interrupt Status
#define	EMAC2_TXFSINT	(1<< 3 )	// TX Frame-Status Interrupt Status
#define	EMAC2_WAKEDET	(1<< 4 )	// Wake-up Detected Status
#define	EMAC2_RXDMAERR	(1<< 5 )	// RX DMA Error Interrupt Status
#define	EMAC2_TXDMAERR	(1<< 6 )	// TX DMA Error Interrupt Status
#define	EMAC2_STMDONE	(1<< 7 )	// Stn Mgt Frame Xfer Done Interrupt Status

//  EMAC2_RX_STAT	RX Current Frame Status 
//  EMAC2_RX_STKY 	RX Sticky Frame Status 
//  EMAC2_RX_INTENA 	RX Frame-Status Interrupt Enables 
// -------------------------------------------------------
// The following bit definitions apply to all of the above three RX status registers.
#define	EMAC2_RxFrameLength(n) 		((n)&0x7FF)	
#define	EMAC2_ReceiveComplete		(1<< 12 ) 
#define	EMAC2_ReceiveOK			(1<< 13 ) 
#define	EMAC2_FrameTooLong		(1<< 14 ) 
#define	EMAC2_AlignmentError		(1<< 15 ) 
#define	EMAC2_FrameCRCError		(1<< 16 ) 
#define	EMAC2_LengthError		(1<< 17 ) 
#define	EMAC2_FrameFragment		(1<< 18 ) 
#define	EMAC2_AddressFilterFailed	(1<< 19 ) 
#define	EMAC2_DMAOverrun		(1<< 20 ) 
#define	EMAC2_PHYError			(1<< 21 ) 
#define	EMAC2_RxLateCollisionSeen	(1<< 22 ) 
#define	EMAC2_OutOfRangeLengthField	(1<< 23 ) 
#define	EMAC2_RxMulticast		(1<< 24 ) 
#define	EMAC2_RxBroadcast		(1<< 25 ) 
#define	EMAC2_RxControlFrame		(1<< 26 ) 
#define	EMAC2_RxUnsupportedControlFrame	(1<< 27 ) 
#define	EMAC2_FrameType			(1<< 28 ) 
#define	EMAC2_VLAN1Frame		(1<< 29 ) 
#define	EMAC2_VLAN2Frame		(1<< 30 ) 
#define	EMAC2_FrameAccepted		(1<< 31 ) 



//  EMAC2_TX_STAT   	TX Current Frame Status 
//  EMAC2_TX_STKY 	TX Sticky Frame Status 
//  EMAC2_TX_INTENA 	TX Frame-Status Interrupt Enables
// -------------------------------------------------------
// The following bit definitions apply to all of the above three TX status registers.
#define	EMAC2_TransmitComplete		(1<< 0 )
#define	EMAC2_TransmitOK		(1<< 1 )
#define	EMAC2_ExcessiveCollisionError	(1<< 2 )
#define	EMAC2_LateCollisionError	(1<< 3 )
#define	EMAC2_DMAUnderrun		(1<< 4 )
#define	EMAC2_ExcessiveDeferral		(1<< 5 )
#define	EMAC2_TxBroadcast		(1<< 6 )
#define	EMAC2_TxMulticast		(1<< 7 )
#define	EMAC2_TxUnicast			0	// just for clarity in src code
#define	EMAC2_CollisionCount(n)		(((n)&0xF)<< 8 )
#define	EMAC2_Deferred			(1<< 12 )
#define	EMAC2_NoCarrier			(1<< 13 )
#define	EMAC2_LossOfCarrier		(1<< 14 )
#define	EMAC2_LateCollisionObserved	(1<< 15 )
#define	EMAC2_TXFrameLength(n)		(((n)&0x7FF)<< 16 )

// The error word that is reported back over DMA when you generate a 
// TX DMA direction error during the data descriptor.  We're
// being asked erroneously to drive dab_data, so this is the value we drive.
#define EMAC2_TxDMADirErrSts	(EMAC2_TransmitComplete | EMAC2_DMAUnderrun)

//  EMAC2_MMC_CTL	MMC Counter Control Register 
// -------------------------------------------------------
#define	EMAC2_RSTC	(1<< 0 )	// Reset All Counters (write-1, reads 0)
#define	EMAC2_CROLL	(1<< 1 )	// Counter Rollover Enable
#define	EMAC2_CCOR	(1<< 2 )	// Counter Clear-On-Read Mode
#define	EMAC2_MMCE	(1<< 3 )	// Enable MMC Counters


//  EMAC2_MMC_RXINT	MMC RX Interrupt Status Register 
//  EMAC2_MMC_RXSTAT 	MMC RX Interrupt Enable Register 
// -------------------------------------------------------
//#define	EMAC2_	(1<< 31 )	// 

//  EMAC2_MMC_TXINT	MMC TX Interrupt Status Register 
//  EMAC2_MMC_TXSTAT 	MMC TX Interrupt Enable Register
// -------------------------------------------------------
//#define	EMAC2_	(1<< 31 )	// 




// Put one or both of these SETUP_EBIU's in @main, early in the program and before any DMA.
// initialize EBIU 
// PSSE Enable; TWR = 1; PSM = 0; TRCD =3; TRP = 2; TRAS = 2;  CL = 2; SCTLE = Disabled
// EBCAW = 1 (9bits); EBSZ = 1 (32MB); EBE = 1 (Enabled)
// PSSE Enable; TWR = 1; PSM = 0; TRCD =3; TRP = 2; TRAS = 2;  CL = 2; SCTLE = Enabled
//#define SETUP_EBIU \
//	    write( EBIU_SDGCTL, 0x8089_9088, 32bit ); \
//	    write( EBIU_SDBCTL, 0x0000_0017, 32bit ); \
//	    write( EBIU_SDGCTL, 0x8089_9089, 32bit ) \
 
// Put one or both of these SETUP_EBIU's in @main, early in the program and before any DMA.
// initialize EBIU 
// PSSE Enable; TWR = 1; PSM = 0; TRCD =3; TRP = 4; TRAS = 4;  CL = 2; SCTLE = Disabled
// EBCAW = 1 (9bits); EBSZ = 1 (32MB); EBE = 1 (Enabled)
// PSSE Enable; TWR = 1; PSM = 0; TRCD =3; TRP = 2; TRAS = 2;  CL = 2; SCTLE = Enabled
#define SETUP_EBIU \
	    write( EBIU_SDGCTL, 0x8091_A108, 32bit ); \
	    write( EBIU_SDBCTL, 0x0000_0017, 32bit ); \
	    write( EBIU_SDGCTL, 0x8091_A109, 32bit ) \


// Initializes EBIU Asynchronous memory interface
// Enable all banks (0-3)
// BWAT = 1, BRAT = 1, BHT = 1, BST = 1, BTT = 1, BRDYPOL = 1, BRDYEN = Enabled	
#define SETUP_EBIU_ASM \
	    write( EBIU_AMGCTL, 0x00FA ); \
	    write( EBIU_AMBCTL0, 0x1156_1156, 32bit ); \
	    write( EBIU_AMBCTL1, 0x1156_1156, 32bit ) \

	    
// -----------------------------------------------------------------------
//                     PHY REGISTER NAMES				//
// -----------------------------------------------------------------------


#define PHYREG_MODECTL		0x0000
#define PHYREG_MODESTAT		0x0001
#define PHYREG_PHYID1		0x0002
#define PHYREG_PHYID2		0x0003
#define PHYREG_ANAR			0x0004
#define PHYREG_ANLPAR		0x0005
#define PHYREG_ANER			0x0006
#define PHYREG_NSR			0x0010
#define PHYREG_LBREMR		0x0011
#define PHYREG_REC			0x0012
#define PHYREG_10CFG		0x0013
#define PHYREG_PHY1_1		0x0014
#define PHYREG_PHY1_2		0x0015
#define PHYREG_PHY2			0x0016
#define PHYREG_TW_1			0x0017
#define PHYREG_TW_2			0x0018
#define PHYREG_TEST			0x0019