pll_setup.c

实现在指定视频服务器下的视频点播

/******************************************************************************/
//
// Name: 	BF533 EZ-KIT PLL Setup
//
/******************************************************************************

(C) Copyright 2003 - Analog Devices, Inc.  All rights reserved.

File Name:	SDRAM_Config.c

Date Modified:	7/02/03		TL		Rev 0.1

Software:       VisualDSP++3.1

Hardware:		ADSP-BF533 EZ-KIT Board

Special Connections:  None

Purpose:		The file sets up the PLL speeds
				
				

*********************************************************************************/


#include <cdefBF533.h>
#include <ccblkfn.h>
#include <sysreg.h>


void Init_PLL(void)
{
	volatile int test=0;

	// Initialize System Configuration Register
	//  enable cycle counter, disable supervisor single step
	sysreg_write(reg_SYSCFG, 0x32);

	*pSIC_IWR |= 0x1;		// enable PLL wakeup

	// The system crystal on the Braemar BUB is at 27.0 MHz
	
//	// default settings: CCLK = 270.0 MHz, SCLK = 54.0 MHz 
//	*pPLL_CTL =  0x1400;	// MSEL= x10,  DF= %1
//	*pPLL_DIV =  0x0005;	// CSEL= %1, SSEL= %5


//	// fast CCLK, slow SCLK: CCLK = 351.0 MHz, SCLK = 25.071 MHz
//	*pPLL_CTL =  0x1A00;	// MSEL= x13,  DF= %1
//	*pPLL_DIV =  0x000E;	// CSEL= %1, SSEL= %14

	// fast CCLK, fast SCLK: CCLK = 526.5 MHz, SCLK = 131.625 MHz 
//	*pPLL_CTL =  0x4E01;	// MSEL= x39,  DF= %2
//	*pPLL_DIV =  0x0004;	// CSEL= %1, SSEL= %4


		// 537 EZ-Kit Settings fast CCLK, fast SCLK: CCLK = 526.5 MHz, SCLK = 131.625 MHz 
	*pPLL_CTL =  0x3000;	// MSEL= x39,  DF= %2
	*pPLL_DIV =  0x0005;	// CSEL= %1, SSEL= %4
	
	
	*pVR_CTL = 0x40db;

	ssync();
	idle();


}//end Init_PLL