mac_definition.h

实现在指定视频服务器下的视频点播

#ifndef  __MAC_DEFINITION_DEFINED
	#define __MAC_DEFINITION_DEFINED

//--------------------------------------------------------------------------//
// Header files																//
//--------------------------------------------------------------------------//
#include <sys\exception.h>
#include <cdefBF537.h>
#include <ccblkfn.h>
#include <sysreg.h>
#include "globals.h"
//--------------------------------------------------------------------------//
// Symbolic constants														//
//--------------------------------------------------------------------------//


//typedef unsigned long  int u32;
//typedef unsigned short int u16;
//typedef unsigned      char  u8;

//////////////////////////////////////////////////
//note: this driver is without linked list, 	//
//      that means with one buffer only 		//
//      and therefore TXFRM_SIZE 1500			//
//////////////////////////////////////////////////

//#define TXFRM_SIZE (64-18) //original, because using linked list you are able to transfer a lott of small packets 		
#define TXFRM_SIZE (1576)   // using only one buffer




#define RCVE_BUFSIZE 1576

#define NO_TX_BUFS		1
#define LOOP_TX 		true
#define NO_RX_BUFS		1
#define LOOP_RX			true

#define ADI_DEV_RESERVED_SIZE 18

// PHY-related constants
#define BR_BUB_PHYADD	0x01
#define BR_EZKIT_PHYADD	0x01
#define NO_PHY_REGS     0x20





// mode settings for how the code will run
bool speed100	= true;
bool full_dpx	= true;

bool ip_chksum	= false;
bool rxdwa		= true;
bool rmii		= false;

bool RunFlag	= true;

bool negotiation = true;


#define  XEROX_IDP_PROTOCOL 	0x0600
#define  IP_PROTOCOL   			0x0800
#define  X_25_PROTOCOL 			0x0805
#define  ARP_PROTOCOL  			0x0806
#define  RARP_PROTOCOL 			0x0835
#define  APPLE_TALK_PROTOCOL 	0x809B
#define  NOVELL_PROTOCOL 		0x8137
#define  NOVELL_PROTOCOL_		0x8138
#define  IP6_PROTOCOL  			0x86DD


#define RX_MAC_FRAME 0x1111 		// a random number from me


///////////////////////////////
//  Global declaration
u8 data[RCVE_BUFSIZE];
u8 BroadcastAddr[6] 	= {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF};
u8 MyAddr[6] 			= {0x00,'B','u','B','_','A'};
u8 SrcAddr[6] 			= {0x00,'B','u','B','_','A'};
u8 DstAddr[6] 			= {0xff,0xff,0xff,0xff,0xff,0xff};
u8 rx_src_addr[]	 	= "ABCDEF";
u8 rx_dst_addr[] 		= "ABCDEF";

u32 rx_MAC_protocol;

// keep a history of the status buffers of the last few frames
u32 TxStsHistory[NO_TX_BUFS];
u32 RxStsHistory[NO_RX_BUFS];

// shadow copy of the PHY registers
u16 PHYregs[NO_PHY_REGS];


/*

#ifndef HTONS
	#if BYTE_ORDER == BIG_ENDIAN
		#define HTONS(n) (n)
	#else // BYTE_ORDER == BIG_ENDIAN 
		#define HTONS(n) ((((u16)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8))
	#endif // BYTE_ORDER == BIG_ENDIAN 
#endif // HTONS 

*/

//--------------------------------------------------------------------------//
// global functions														//
//--------------------------------------------------------------------------//

void MemFailure(void)
{
	printf("Failed to allocate some memory\n");
	a:
	goto a;
}


//--------------------------------------------------------------------------//
// global DMA Definition 													//
//--------------------------------------------------------------------------//




////////////////////////////////
// DMA Definition
#define DMA2_NEXT_DESC_PTR		0xFFC00C80	// DMA Channel 2 Next Descriptor Pointer Register
#define DMA2_START_ADDR			0xFFC00C84	// DMA Channel 2 Start Address Register
#define DMA2_CONFIG				0xFFC00C88	// DMA Channel 2 Configuration Register
#define DMA2_X_COUNT			0xFFC00C90	// DMA Channel 2 X Count Register
#define DMA2_X_MODIFY			0xFFC00C94	// DMA Channel 2 X Modify Register
#define DMA2_Y_COUNT			0xFFC00C98	// DMA Channel 2 Y Count Register
#define DMA2_Y_MODIFY			0xFFC00C9C	// DMA Channel 2 Y Modify Register
#define DMA2_CURR_DESC_PTR		0xFFC00CA0	// DMA Channel 2 Current Descriptor Pointer Register
#define DMA2_CURR_ADDR			0xFFC00CA4	// DMA Channel 2 Current Address Register
#define DMA2_IRQ_STATUS			0xFFC00CA8	// DMA Channel 2 Interrupt/Status Register
#define DMA2_PERIPHERAL_MAP		0xFFC00CAC	// DMA Channel 2 Peripheral Map Register
#define DMA2_CURR_X_COUNT		0xFFC00CB0	// DMA Channel 2 Current X Count Register
#define DMA2_CURR_Y_COUNT		0xFFC00CB8	// DMA Channel 2 Current Y Count Register


typedef struct ADI_DMA_CONFIG_REG {
	u16 b_DMA_EN:1;		//0		Enabled
	u16 b_WNR:1;		//1		Direction
	u16 b_WDSIZE:2;		//2:3	Transfer word size	
	u16 b_DMA2D:1;		//4		DMA mode 
	u16 b_RESTART:1;	//5		Retain FIFO
	u16 b_DI_SEL:1;		//6		Data interrupt timing select
	u16 b_DI_EN:1;		//7		Data interrupt enabled
	u16 b_NDSIZE:4;		//8:11	Flex descriptor size
	u16 b_FLOW:3;		//12:14	Flow		
} ADI_DMA_CONFIG_REG;

typedef struct dma_registers {
	struct dma_registers*	NEXT_DESC_PTR;
	unsigned long int		START_ADDR;
	ADI_DMA_CONFIG_REG		CONFIG;
} DMA_REGISTERS;

//--------------------------------------------------------------------------//
// global structures														//
//--------------------------------------------------------------------------//

typedef struct adi_emac_staadd_reg {
	u32 b_STABUSY:1;	//0		Busy
	u32 b_STAOP:1;		//1		Direction
	u32 b_STADISPRE:1;	//2		Disable preamble	
	u32 b_STAIE:1;		//3		Sta. Mgmt. Done Irq Enable 
	u32 :2;				//4:5	reserved
	u32 b_REGAD:5;		//6:10	Sta. Reg. Address
	u32 b_PHYAD:5;		//11:15	Sta. PHY  Address
	u32 :16;			//16:31 reserved
} ADI_EMAC_STAADD_REG;

typedef struct adi_ether_frame_buffer {
	u16		NoBytes;		// the no. of following bytes
	u8		Dest[6];		// destination MAC address
	u8		Srce[6];		// source MAC address
	u16		LTfield;		// length/type field
	u8		Data[0];		// payload bytes
} ADI_ETHER_FRAME_BUFFER; 


typedef struct adi_ether_buffer {	
	DMA_REGISTERS			Dma[2];	// first for the frame, second for the status						
	ADI_ETHER_FRAME_BUFFER	*Data;	// pointer to data
	u32	ElementCount;	// data element count
	u32	ElementWidth;	// data element width (in bytes)
	void*	CallbackParameter;// callback flag/pArg value
	u32	ProcessedFlag;	// processed flag
	u32	ProcessedElementCount;
						// # of bytes read in/out
	struct adi_ether_buffer	*pNext;	// next buffer
	void	*PayLoad;		// pointer to IP Payload
	u32	PayloadCount;	// Length of payload
	u32	PayloadWidth;	// Width of payload (in bytes)
	u16	IPHdrChksum;	// the IP header checksum
	u16	IPPayloadChksum;	// the IP header and payload checksum
	u32	StatusWord;		// the frame status word
} ADI_ETHER_BUFFER;


//--------------------------------------------------------------------------//
// crate TX and RX main structure														//
//--------------------------------------------------------------------------//





////////////////////////////////
//		format a TX  buffer
//

ADI_ETHER_BUFFER *SetupTxBuffer(int datasize,unsigned int root)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	unsigned int i;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2])/2;	// ensure a mult. of 4
	
	// setup a frame of datasize bytes + 14 byte ethernet header
	buf = (ADI_ETHER_BUFFER *)malloc(nobytes_buffer+sizeof(ADI_ETHER_FRAME_BUFFER)+datasize);
	if (buf==NULL) MemFailure();
	frmbuf = (ADI_ETHER_FRAME_BUFFER *)(((char *)buf) + nobytes_buffer);
	
	// set up the buffer
	memset(buf,0,nobytes_buffer);
	buf->Data = frmbuf;
	
	//set up first desc to point to transmit frame buffer
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32)buf->Data;
	// config files alrady zero, so 
	// memory read, linear,  retain fifo data, interrupt after whole buffer, 
	// dma interrupt disabled
	buf->Dma[0].CONFIG.b_DMA_EN = 1;		// enabled
	buf->Dma[0].CONFIG.b_WDSIZE = 2;		// wordsize is 32 bits
	buf->Dma[0].CONFIG.b_NDSIZE = 5;		// 5 half words is desc size.
	buf->Dma[0].CONFIG.b_FLOW   = 7;		// large desc flow
	
	
	//set up second desc to point to status word
	buf->Dma[1].NEXT_DESC_PTR = (DMA_REGISTERS*)NULL;
	buf->Dma[1].START_ADDR = (u32)&buf->StatusWord;
	// config files alrady zero, so 
	// linear,  retain fifo data, interrupt after whole buffer, 
	// dma interrupt disabled
	buf->Dma[1].CONFIG.b_DMA_EN = 1;		// enabled
	buf->Dma[1].CONFIG.b_WNR    = 1;		// write to memory
	buf->Dma[1].CONFIG.b_WDSIZE = 2;		// wordsize is 32 bits
	buf->Dma[1].CONFIG.b_NDSIZE = 0;		// 0 when FLOW is 0.
	buf->Dma[1].CONFIG.b_FLOW   = 0;		// stop
	
	// set up the frame buffer
	frmbuf->NoBytes = 14+datasize; // ethernet header
//	memcpy(frmbuf->Dest,DstAddr,6);
//	memcpy(frmbuf->Srce,SrcAddr,6);
	frmbuf->LTfield = datasize;
	
//	for(i=0; i<datasize; i++) frmbuf->Data[i] = (u8)(i+root)&0xff;
	for(i=0; i<datasize; i++) frmbuf->Data[i] = 0x0;
	
	return buf;
	
}


////////////////////////////
//		setup a RX  buffer
//

ADI_ETHER_BUFFER *SetupRxBuffer(bool chksum)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	int i;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2])/2;	// ensure a mult. of 4
	
	// setup a frame of datasize bytes + 14 byte ethernet header
	buf = (ADI_ETHER_BUFFER *)malloc(nobytes_buffer+sizeof(ADI_ETHER_FRAME_BUFFER)+RCVE_BUFSIZE);
	if (buf==NULL) MemFailure();
	frmbuf = (ADI_ETHER_FRAME_BUFFER *)(((char *)buf) + nobytes_buffer);
	
	// set up the buffer
	memset(buf,0,nobytes_buffer);	// clear ether buf
	buf->Data = frmbuf;
	memset(frmbuf, 0xfe, RCVE_BUFSIZE);	// background pattern for data buf
	
	//set up first desc to point to receive frame buffer
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32)buf->Data;
	// config files alrady zero, so 
	// linear,  retain fifo data, interrupt after whole buffer, 
	// dma interrupt disabled
	buf->Dma[0].CONFIG.b_DMA_EN = 1;		// enabled
	buf->Dma[0].CONFIG.b_WNR    = 1;		// write to memory
	buf->Dma[0].CONFIG.b_WDSIZE = 2;		// wordsize is 32 bits
	buf->Dma[0].CONFIG.b_NDSIZE = 5;		// 5 half words is desc size.
	buf->Dma[0].CONFIG.b_FLOW   = 7;		// large desc flow
	
	
	//set up second desc to point to status word
	buf->Dma[1].NEXT_DESC_PTR = (DMA_REGISTERS*)NULL;
	if (chksum) {
		buf->Dma[1].START_ADDR = (u32)&buf->IPHdrChksum;
	} else {
		buf->Dma[1].START_ADDR = (u32)&buf->StatusWord;
	}
	// config files already zero, so 
	// linear,  retain fifo data, interrupt after whole buffer, 
	// dma interrupt disabled, and zero size next desc
	buf->Dma[1].CONFIG.b_DMA_EN = 1;		// enabled
	buf->Dma[1].CONFIG.b_WNR    = 1;		// write to memory
	buf->Dma[1].CONFIG.b_WDSIZE = 2;		// wordsize is 32 bits
	buf->Dma[1].CONFIG.b_FLOW   = 0;		// stop
	
	
	return buf;
	
}



//--------------------------------------------------------------------------//
// Global variables															//
//--------------------------------------------------------------------------//
/*
extern int iChannel0LeftIn;
extern int iChannel0RightIn;
extern int iChannel0LeftOut;
extern int iChannel0RightOut;
extern int iChannel1LeftIn;
extern int iChannel1RightIn;
extern int iChannel1LeftOut;
extern int iChannel1RightOut;
extern volatile short sCodec1836TxRegs[];
extern volatile int iRxBuffer1[];
extern volatile int iTxBuffer1[];
*/

// global struct , different of the original

ADI_ETHER_BUFFER 		*txbuf,
						*txfst,
				 		*txlst=NULL,
						*rxbuf,
						*rxfst,
						*rxlst=NULL;
					
//ADI_ETHER_FRAME_BUFFER 	*frmbuf;
//uip_icmpip_hdr 			*frmbuf_ip_cmp;
//ARP_HDR 				*frmbuf_arp;
//UIP_UDPIP_HDR 			*frmbuf_ip_udp;
//UIP_TCPIP_HDR 			*frmbuf_ip_tcp;


//--------------------------------------------------------------------------//
// Prototypes																//
//--------------------------------------------------------------------------//
// in file Initialisation.c


#endif //__MAC_DEFINITION_DEFINED