📄 install.a51
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ENDIF
T2REL EQU 10000H-((CPU_CLOCK+(DIVFACTOR/2))/DIVFACTOR)
MOV RCAP2H,#HIGH(T2REL)
MOV TH2,#HIGH(T2REL)
MOV RCAP2L,#LOW(T2REL)
MOV TL2,#LOW(T2REL)
MOV T2CON,#34H ; set RCLK/TCLK/TR2
MOV SCON,#01011010B ; Init Serial Interface
ENDIF
MOV AUXR,#_AUXR ; Configure T89C51RC2
JMP Mon51
ENDIF
IF (SERIAL = 2)
;********************************************************************
;* Using external UART 16450/16550 *
;********************************************************************
DIVFACTOR EQU BAUDRATE*16
BAUDDIV EQU (EX_UART_CLK+(DIVFACTOR/2))/DIVFACTOR
InitSerial:
MOV DPTR,#EX_UART_ADR+3
MOV A,#83H ; Select Baudrate Registers
MOVX @DPTR,A
MOV DPTR,#EX_UART_ADR
MOV A,#LOW (BAUDDIV)
MOVX @DPTR,A
INC DPTR
MOV A,#HIGH (BAUDDIV)
MOVX @DPTR,A
MOV DPTR,#EX_UART_ADR+3
MOV A,#03H ; Mode: 8-bit, 1 stop, no parity
MOVX @DPTR,A
MOV DPTR,#EX_UART_ADR+1
CLR A
MOVX @DPTR,A ; disable all interrupts
MOV DPTR,#EX_UART_ADR+4
MOVX @DPTR,A
MOV AUXR,#_AUXR ; Configure T89C51RC2
MOV P1,#01H
JMP Mon51
ENDIF
IF (SERIAL = 2)
;********************************************************************
;* Interface via external UART 16450/16550 *
;********************************************************************
SER_INT_ADR EQU 000H ; ADDRESS OF SERIAL INTERRUPT VECTOR.
; Set to 0 for no interrupt
INSTAT: PUSH DPL ; INPUT STATUS OF SERIAL INTERFACE
PUSH DPH
PUSH ACC
MOV DPTR,#EX_UART_ADR+5 ; LSR
MOVX A,@DPTR ; Check if Ready
MOV C,ACC.0
POP ACC
POP DPH
POP DPL
RET
OUTSTAT: PUSH DPL ; OUTPUT STATUS OF SERIAL INTERFACE
PUSH DPH
PUSH ACC
MOV DPTR,#EX_UART_ADR+5 ; LSR
MOVX A,@DPTR ; Check if Ready
MOV C,ACC.5
POP ACC
POP DPH
POP DPL
RET
INCHAR: PUSH DPL ; CHARACTER INPUT-ROUTINE
PUSH DPH
MOV DPTR,#EX_UART_ADR
MOVX A,@DPTR
ORL P1,#02H
POP DPH
POP DPL
RET
OUTCHAR: PUSH DPL ; CHARACTER OUTPUT-ROUTINE
PUSH DPH
MOV DPTR,#EX_UART_ADR
MOVX @DPTR,A
ORL P1,#04H
POP DPH
POP DPL
RET
CLR_TI: ; CLEAR SERIAL TRANSMIT INTERRUPT FLAG
RET
SET_TI: ; SET SERIAL TRANSMIT INTERRUPT FLAG
RET
CLR_RI: ; CLEAR SERIAL RECEIVE INTERRUPT FLAG
RET
CLR_SER_IE: ; CLEAR SERIAL INTERRUPT ENABLE FLAG
RET
SET_SER_IE: ; SET SERIAL INTERRUPT ENABLE FLAG
RET
ELSE
;********************************************************************
;* Interface via standard 8051 UART *
;********************************************************************
SER_INT_ADR EQU 23H ; ADDRESS OF SERIAL INTERRUPT VECTOR
INSTAT: MOV C,RI ; INPUT STATUS OF SERIAL INTERFACE
RET
OUTSTAT: MOV C,TI ; OUTPUT STATUS OF SERIAL INTERFACE
RET
INCHAR: MOV A,SBUF ; CHARACTER INPUT-ROUTINE
RET
OUTCHAR: MOV SBUF,A ; CHARACTER OUTPUT-ROUTINE
RET
CLR_TI: CLR TI ; CLEAR SERIAL TRANSMIT INTERRUPT FLAG
RET
SET_TI: SETB TI ; SET SERIAL TRANSMIT INTERRUPT FLAG
RET
CLR_RI: CLR RI ; CLEAR SERIAL RECEIVE INTERRUPT FLAG
RET
CLR_SER_IE: CLR ES ; CLEAR SERIAL INTERRUPT ENABLE FLAG
RET
SET_SER_IE: SETB ES ; SET SERIAL INTERRUPT ENABLE FLAG
RET
ENDIF
BEFORE_GO: ; this code is executed before a
RET ; a go or proc step is executed
AFTER_GO: ; this code is executed after a go
RET ; command (when a breakpoint was set)
IF (FLASH_PAGESIZE <> 0)
;*********************************************************************
;* Flash programming functions for ATMEL T89C51RB2/RC2/CC01 devices *
;*********************************************************************
FBUSY_MSK EQU 001h
FMOD_MSK EQU 006h
FPS_MSK EQU 008h
FPL_MSK EQU 0F0h
FMOD_USER_MSK EQU 000h
FMOD_XROW_MSK EQU 002h
FMOD_FUSE_MSK EQU 004h
SEL_USER_CL EQU 008h
FPL_S0 EQU 050h
FPL_S1 EQU 0A0h
DATA_AREA SEGMENT DATA
RSEG DATA_AREA
BLOCK_LEN: DS 1
S_ADR_L: DS 1
S_ADR_H: DS 1
B_ADR_L: DS 1
B_ADR_H: DS 1
XDATA_AREA SEGMENT XDATA
RSEG XDATA_AREA
F_BUFFER: DS 128
RSEG INSTALLCODE
PRE_PROG: MOV BLOCK_LEN,A ; Prepare for Flash programming
MOV S_ADR_L,DPL ; A=block length DPTR=first address
MOV S_ADR_H,DPH ; This function must not take much time! (no flash erase!)
MOV B_ADR_L,#LOW(F_BUFFER)
MOV B_ADR_H,#HIGH(F_BUFFER)
RET
LD_FPAGE: PUSH DPL ; load data into flash page or ram for programming
PUSH DPH
MOV DPL,B_ADR_L
MOV DPH,B_ADR_H
MOVX @DPTR,A
INC DPTR
MOV B_ADR_L,DPL
MOV B_ADR_H,DPH
POP DPH
POP DPL
SETB C ; set C flag to suppresses immediate code verify
RET ; C flag set suppresses code verify
POST_PROG: ; Finish Flash programming
ORL AUXR1,#20h ; MAP boot memory
MOV R1,#09h
MOV A,BLOCK_LEN ; number of bytes to flash
MOV DPL,S_ADR_L
MOV DPH,S_ADR_H
INC AUXR1
MOV DPTR,#F_BUFFER
INC AUXR1
LCALL 0FFF0H ; Common API entry point in the bootloader
ANL AUXR1, #0DFh ; UNMAP BOOT MEMORY
RET
; write one byte into flash
WR_CODE: PUSH AR1 ; Save regiters R1 R2 R4 R6
MOV R1, #02h ; Prepare for API write byte
PUSH AR2
PUSH AR4
PUSH AR6
PUSH ACC
ORL AUXR1,#20h ; MAP boot memory
LCALL 0FFF0h ; Common API entry point in the bootloader
ANL AUXR1, #0DFh ; UNMAP BOOT MEMORY
POP ACC
POP AR6
POP AR4
POP AR2
POP AR1
RET
ELSE
; Dummy flash functions when application is loaded into v.Neumann RAM
PRE_PROG: RET ; prepare flash for programming
LD_FPAGE: MOVX @DPTR,A ; write one byte into v.Neumann wired RAM
CLR C ; clear C flag to force immediate code verification
RET
POST_PROG: RET ; Finish Flash programming
WR_CODE: MOVX @DPTR,A ; write one byte into v.Neumann wired RAM
RET
ENDIF
SER_INT_ADR_OFF EQU (INT_ADR_OFF + SER_INT_ADR)
XDATA_BEGIN SEGMENT XDATA AT XDATA_START
RSEG XDATA_BEGIN
XDATA_START_ADR:DS 1 ; define one dummy byte
IF (FLASH_PAGESIZE <> 0)
CODE_AREA SEGMENT CODE
RSEG CODE_AREA
ELSE
XDATA_AREA SEGMENT XDATA
RSEG XDATA_AREA
ENDIF
EXECBUFF: DS 9
END
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