c8051f060.h

Keil uVision2

/*---------------------------------------------------------------------------
; Copyright (C) 2002 CYGNAL INTEGRATED PRODUCTS, INC.
; All rights reserved.
;
;
; FILE NAME: C8051F060.H
; TARGET MCUs: C8051F060, F061, F062, F063
; DESCRIPTION: Register/bit definitions for the C8051F060 product family.
;
; REVISION 1.2
;
;---------------------------------------------------------------------------*/

/*  BYTE Registers  */

sfr P0            = 0x80; /* PORT 0 LATCH */
sfr SP            = 0x81; /* STACK POINTER */
sfr DPL           = 0x82; /* DATA POINTER LOW */
sfr DPH           = 0x83; /* DATA POINTER HIGH */
sfr SFRPAGE       = 0x84; /* SFR PAGE REGISTER */
sfr SFRNEXT       = 0x85; /* SFR PAGE REGISTER */
sfr SFRLAST       = 0x86; /* SFR PAGE STACK ACCESS REGISTER */
sfr PCON          = 0x87; /* POWER CONTROL */
sfr CPT0CN        = 0x88; /* COMPARATOR 0 CONTROL */
sfr CPT1CN        = 0x88; /* COMPARATOR 1 CONTROL */
sfr CPT2CN        = 0x88; /* COMPARATOR 2 CONTROL */
sfr TCON          = 0x88; /* TIMER/COUNTER CONTROL */
sfr CPT0MD        = 0x89; /* COMPARATOR 0 CONFIGURATION */
sfr CPT1MD        = 0x89; /* COMPARATOR 1 CONFIGURATION */
sfr CPT2MD        = 0x89; /* COMPARATOR 2 CONFIGURATION */
sfr TMOD          = 0x89; /* TIMER/COUNTER MODE */
sfr OSCICN        = 0x8A; /* INTERNAL OSCILLATOR CONTROL */
sfr TL0           = 0x8A; /* TIMER/COUNTER 0 LOW */
sfr OSCICL        = 0x8B; /* INTERNAL OSCILLATOR CALIBRATION */
sfr TL1           = 0x8B; /* TIMER/COUNTER 1 LOW */
sfr OSCXCN        = 0x8C; /* EXTERNAL OSCILLATOR CONTROL */
sfr TH0           = 0x8C; /* TIMER/COUNTER 0 HIGH */
sfr TH1           = 0x8D; /* TIMER/COUNTER 1 HIGH */
sfr CKCON         = 0x8E; /* CLOCK CONTROL */
sfr PSCTL         = 0x8F; /* PROGRAM STORE R/W CONTROL */
sfr P1            = 0x90; /* PORT 1 LATCH */
sfr SSTA0         = 0x91; /* UART 0 STATUS */
sfr SFRPGCN       = 0x96; /* SFR PAGE CONTROL REGISTER */
sfr CLKSEL        = 0x97; /* OSCILLATOR CLOCK SELECTION REGISTER */
sfr SCON0         = 0x98; /* UART 0 CONTROL */
sfr SCON1         = 0x98; /* UART 1 CONTROL */
sfr SBUF0         = 0x99; /* UART 0 DATA BUFFER */
sfr SBUF1         = 0x99; /* UART 1 DATA BUFFER */
sfr SPI0CFG       = 0x9A; /* SPI CONFIGURATION */
sfr SPI0DAT       = 0x9B; /* SPI DATA */
sfr P4MDOUT       = 0x9C; /* PORT 4 OUTPUT MODE CONFIGURATION */
sfr P5MDOUT       = 0x9D; /* PORT 5 OUTPUT MODE CONFIGURATION */
sfr SPI0CKR       = 0x9D; /* SPI CLOCK RATE CONTROL */
sfr P6MDOUT       = 0x9E; /* PORT 6 OUTPUT MODE CONFIGURATION */
sfr P7MDOUT       = 0x9F; /* PORT 7 OUTPUT MODE CONFIGURATION */
sfr P2            = 0xA0; /* PORT 2 LATCH */
sfr EMI0TC        = 0xA1; /* EMIF TIMING CONTROL */
sfr EMI0CN        = 0xA2; /* EMIF CONTROL */
sfr EMI0CF        = 0xA3; /* EMIF CONFIGURATION */
sfr P0MDOUT       = 0xA4; /* PORT 0 OUTPUT MODE CONFIGURATION */
sfr P1MDOUT       = 0xA5; /* PORT 1 OUTPUT MODE CONFIGURATION */
sfr P2MDOUT       = 0xA6; /* PORT 2 OUTPUT MODE CONFIGURATION */
sfr P3MDOUT       = 0xA7; /* PORT 3 OUTPUT MODE CONFIGURATION */
sfr IE            = 0xA8; /* INTERRUPT ENABLE */
sfr SADDR0        = 0xA9; /* UART 0 SLAVE ADDRESS */
sfr P1MDIN        = 0xAD; /* PORT 1 INPUT MODE */
sfr P2MDIN        = 0xAE; /* PORT 2 INPUT MODE */
sfr P3            = 0xB0; /* PORT 3 LATCH */
sfr FLACL         = 0xB7; /* FLASH ACCESS LIMIT */
sfr FLSCL         = 0xB7; /* FLASH SCALE */
sfr IP            = 0xB8; /* INTERRUPT PRIORITY */
sfr SADEN0        = 0xB9; /* UART 0 SLAVE ADDRESS ENABLE */
sfr ADC0CPT       = 0xBA; /* ADC0 CALIBRATION POINTER */
sfr AMX2CF        = 0xBA; /* ADC2 ANALOG MULTIPLEXER CONFIGURATION */
sfr ADC0CCF       = 0xBB; /* ADC0 CALIBRATION COEFFICIENT */
sfr AMX0SL        = 0xBB; /* ADC0 MULTIPLEXER CHANNEL SELECT */
sfr AMX2SL        = 0xBB; /* ADC2 ANALOG MULTIPLEXER CHANNEL SELECT */
sfr ADC0CF        = 0xBC; /* ADC0 CONFIGURATION */
sfr ADC1CF        = 0xBC; /* ADC1 CONFIGURATION */
sfr ADC2CF        = 0xBC; /* ADC2 CONFIGURATION */
sfr ADC0L         = 0xBE; /* ADC0 DATA WORD LOW */
sfr ADC1L         = 0xBE; /* ADC1 DATA WORD LOW */
sfr ADC2L         = 0xBE; /* ADC2 DATA WORD LOW */
sfr ADC0H         = 0xBF; /* ADC0 DATA WORD HIGH */
sfr ADC1H         = 0xBF; /* ADC1 DATA WORD HIGH */
sfr ADC2H         = 0xBF; /* ADC2 DATA WORD HIGH */
sfr CAN0STA       = 0xC0; /* CAN0 STATUS */
sfr SMB0CN        = 0xC0; /* SMBUS CONTROL */
sfr SMB0STA       = 0xC1; /* SMBUS STATUS */
sfr SMB0DAT       = 0xC2; /* SMBUS DATA */
sfr SMB0ADR       = 0xC3; /* SMBUS SLAVE ADDRESS */
sfr ADC0GTL       = 0xC4; /* ADC0 GREATER-THAN LOW */
sfr ADC2GTL       = 0xC4; /* ADC2 GREATER-THAN LOW */
sfr ADC0GTH       = 0xC5; /* ADC0 GREATER-THAN HIGH */
sfr ADC2GTH       = 0xC5; /* ADC2 GREATER-THAN HIGH */
sfr ADC0LTL       = 0xC6; /* ADC0 LESS-THAN LOW */
sfr ADC2LTL       = 0xC6; /* ADC2 LESS-THAN LOW */
sfr ADC0LTH       = 0xC7; /* ADC0 LESS-THAN HIGH */
sfr ADC2LTH       = 0xC7; /* ADC2 LESS-THAN HIGH */
sfr P4            = 0xC8; /* PORT 4 LATCH */
sfr TMR2CN        = 0xC8; /* TIMER/COUNTER 2 CONTROL */
sfr TMR3CN        = 0xC8; /* TIMER/COUNTER 3 CONTROL */
sfr TMR4CN        = 0xC8; /* TIMER/COUNTER 4 CONTROL */
sfr TMR2CF        = 0xC9; /* TIMER/COUNTER 2 CONFIGURATION */
sfr TMR3CF        = 0xC9; /* TIMER/COUNTER 3 CONFIGURATION */
sfr TMR4CF        = 0xC9; /* TIMER/COUNTER 4 CONFIGURATION */
sfr RCAP2L        = 0xCA; /* TIMER/COUNTER 2 CAPTURE/RELOAD LOW */
sfr RCAP3L        = 0xCA; /* TIMER/COUNTER 3 CAPTURE/RELOAD LOW */
sfr RCAP4L        = 0xCA; /* TIMER/COUNTER 4 CAPTURE/RELOAD LOW */
sfr RCAP2H        = 0xCB; /* TIMER/COUNTER 2 CAPTURE/RELOAD HIGH */
sfr RCAP3H        = 0xCB; /* TIMER/COUNTER 3 CAPTURE/RELOAD HIGH */
sfr RCAP4H        = 0xCB; /* TIMER/COUNTER 4 CAPTURE/RELOAD HIGH */
sfr TMR2L         = 0xCC; /* TIMER/COUNTER 2 LOW */
sfr TMR3L         = 0xCC; /* TIMER/COUNTER 3 LOW */
sfr TMR4L         = 0xCC; /* TIMER/COUNTER 4 LOW */
sfr TMR2H         = 0xCD; /* TIMER/COUNTER 2 HIGH */
sfr TMR3H         = 0xCD; /* TIMER/COUNTER 3 HIGH */
sfr TMR4H         = 0xCD; /* TIMER/COUNTER 4 HIGH */
sfr SMB0CR        = 0xCF; /* SMBUS CLOCK RATE */
sfr PSW           = 0xD0; /* PROGRAM STATUS WORD */
sfr REF0CN        = 0xD1; /* VOLTAGE REFERENCE CONTROL 0 */
sfr REF1CN        = 0xD1; /* VOLTAGE REFERENCE CONTROL 1 */
sfr REF2CN        = 0xD1; /* VOLTAGE REFERENCE CONTROL 2 */
sfr DAC0L         = 0xD2; /* DAC0 LOW */
sfr DAC1L         = 0xD2; /* DAC1 LOW */
sfr DAC0H         = 0xD3; /* DAC0 HIGH */
sfr DAC1H         = 0xD3; /* DAC1 HIGH */
sfr DAC0CN        = 0xD4; /* DAC0 CONTROL */
sfr DAC1CN        = 0xD4; /* DAC1 CONTROL */
sfr CAN0DATL      = 0xD8; /* CAN0 DATA LOW */
sfr DMA0CN        = 0xD8; /* DMA0 CONTROL */
sfr P5            = 0xD8; /* PORT 5 LATCH */
sfr PCA0CN        = 0xD8; /* PCA CONTROL */
sfr CAN0DATH      = 0xD9; /* CAN0 DATA HIGH */
sfr DMA0DAL       = 0xD9; /* DMA0 DATA ADDRESS BEGINNING LOW BYTE */
sfr PCA0MD        = 0xD9; /* PCA MODE */
sfr CAN0ADR       = 0xDA; /* CAN0 ADDRESS */
sfr DMA0DAH       = 0xDA; /* DMA0 DATA ADDRESS BEGINNING HIGH BYTE */
sfr PCA0CPM0      = 0xDA; /* PCA MODULE 0 MODE REGISTER */
sfr CAN0TST       = 0xDB; /* CAN0 TEST */
sfr DMA0DSL       = 0xDB; /* DMA0 DATA ADDRESS POINTER LOW BYTE */
sfr PCA0CPM1      = 0xDB; /* PCA MODULE 1 MODE REGISTER */
sfr DMA0DSH       = 0xDC; /* DMA0 DATA ADDRESS POINTER HIGH BYTE */
sfr PCA0CPM2      = 0xDC; /* PCA MODULE 2 MODE REGISTER */
sfr DMA0IPT       = 0xDD; /* DMA0 INSTRUCTION WRITE ADDRESS */
sfr PCA0CPM3      = 0xDD; /* PCA MODULE 3 MODE REGISTER */
sfr DMA0IDT       = 0xDE; /* DMA0 INSTRUCTION WRITE DATA */
sfr PCA0CPM4      = 0xDE; /* PCA MODULE 4 MODE REGISTER */
sfr PCA0CPM5      = 0xDF; /* PCA MODULE 5 MODE REGISTER */
sfr ACC           = 0xE0; /* ACCUMULATOR */
sfr PCA0CPL5      = 0xE1; /* PCA CAPTURE 5 LOW */
sfr XBR0          = 0xE1; /* PORT I/O CROSSBAR CONTROL 0 */
sfr PCA0CPH5      = 0xE2; /* PCA CAPTURE 5 HIGH */
sfr XBR1          = 0xE2; /* PORT I/O CROSSBAR CONTROL 1 */
sfr XBR2          = 0xE3; /* PORT I/O CROSSBAR CONTROL 2 */
sfr XBR3          = 0xE4; /* PORT I/O CROSSBAR CONTROL 3 */
sfr EIE1          = 0xE6; /* EXTENDED INTERRUPT ENABLE 1 */
sfr EIE2          = 0xE7; /* EXTENDED INTERRUPT ENABLE 2 */
sfr ADC0CN        = 0xE8; /* ADC0 CONTROL */
sfr ADC1CN        = 0xE8; /* ADC1 CONTROL */
sfr ADC2CN        = 0xE8; /* ADC2 CONTROL */
sfr P6            = 0xE8; /* PORT 6 LATCH */
sfr PCA0CPL2      = 0xE9; /* PCA CAPTURE 2 LOW */
sfr PCA0CPH2      = 0xEA; /* PCA CAPTURE 2 HIGH */
sfr PCA0CPL3      = 0xEB; /* PCA CAPTURE 3 LOW */
sfr PCA0CPH3      = 0xEC; /* PCA CAPTURE 3 HIGH */
sfr PCA0CPL4      = 0xED; /* PCA CAPTURE 4 LOW */
sfr PCA0CPH4      = 0xEE; /* PCA CAPTURE 4 HIGH */
sfr RSTSRC        = 0xEF; /* RESET SOURCE */
sfr B             = 0xF0; /* B REGISTER */
sfr EIP1          = 0xF6; /* EXTERNAL INTERRUPT PRIORITY 1 */
sfr EIP2          = 0xF7; /* EXTERNAL INTERRUPT PRIORITY 2 */
sfr CAN0CN        = 0xF8; /* CAN0 CONTROL */
sfr DMA0CF        = 0xF8; /* DMA0 CONFIGURATION */
sfr P7            = 0xF8; /* PORT 7 LATCH */
sfr SPI0CN        = 0xF8; /* SPI CONTROL */
sfr DMA0CTL       = 0xF9; /* DMA0 REPEAT COUNTER LIMIT LOW BYTE */
sfr PCA0L         = 0xF9; /* PCA COUNTER LOW */
sfr DMA0CTH       = 0xFA; /* DMA0 REPEAT COUNTER LIMIT HIGH BYTE */
sfr PCA0H         = 0xFA; /* PCA COUNTER HIGH */
sfr DMA0CSL       = 0xFB; /* DMA0 REPEAT COUNTER STATUS LOW BYTE */
sfr PCA0CPL0      = 0xFB; /* PCA CAPTURE 0 LOW */
sfr DMA0CSH       = 0xFC; /* DMA0 REPEAT COUNTER STATUS HIGH BYTE */
sfr PCA0CPH0      = 0xFC; /* PCA CAPTURE 0 HIGH */
sfr DMA0BND       = 0xFD; /* DMA0 INSTRUCTION BOUNDARY */
sfr PCA0CPL1      = 0xFD; /* PCA CAPTURE 1 LOW */
sfr DMA0ISW       = 0xFE; /* DMA0 INSTRUCTION STATUS */
sfr PCA0CPH1      = 0xFE; /* PCA CAPTURE 1 HIGH */
sfr WDTCN         = 0xFF; /* WATCHDOG TIMER CONTROL */


/* Bit Definitions */

/* TCON 0x88 */
sbit TF1 =        0x8F ;  /* TIMER 1 OVERFLOW FLAG */
sbit TR1 =        0x8E ;  /* TIMER 1 ON/OFF CONTROL */
sbit TF0 =        0x8D ;  /* TIMER 0 OVERFLOW FLAG */
sbit TR0 =        0x8C ;  /* TIMER 0 ON/OFF CONTROL */
sbit IE1 =        0x8B ;  /* EXT. INTERRUPT 1 EDGE FLAG */
sbit IT1 =        0x8A ;  /* EXT. INTERRUPT 1 TYPE */
sbit IE0 =        0x89 ;  /* EXT. INTERRUPT 0 EDGE FLAG */
sbit IT0 =        0x88 ;  /* EXT. INTERRUPT 0 TYPE */

/* CPT0CN 0x88 */
sbit CP0EN =      0x8F ;  /* COMPARATOR 0 ENABLE */
sbit CP0OUT =     0x8E ;  /* COMPARATOR 0 OUTPUT */
sbit CP0RIF =     0x8D ;  /* COMPARATOR 0 RISING EDGE INTERRUPT */
sbit CP0FIF =     0x8C ;  /* COMPARATOR 0 FALLING EDGE INTERRUPT */