📄 dr80390xp.h
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sbit SM1 = SCON0^6;
sbit SM0 = SCON0^7;
#endif
/* IE */
sbit EX0 = IE^0;
#ifdef TIMERS01_ENABLED
sbit ET0 = IE^1;
#endif
sbit EX1 = IE^2;
#ifdef TIMERS01_ENABLED
sbit ET1 = IE^3;
#endif
#ifdef UART0_ENABLED
sbit ES0 = IE^4;
sbit ES = IE^4;
#endif
#ifdef TIMER2_ENABLED
sbit ET2 = IE^5;
#endif
#ifdef UART1_ENABLED
sbit ES1 = IE^6;
#endif
sbit EA = IE^7;
/* IP */
sbit PX0 = IP^0;
#ifdef TIMERS01_ENABLED
sbit PT0 = IP^1;
#endif
sbit PX1 = IP^2;
#ifdef TIMERS01_ENABLED
sbit PT1 = IP^3;
#endif
#ifdef UART0_ENABLED
sbit PS0 = IP^4;
sbit PS = IP^4;
#endif
#ifdef TIMER2_ENABLED
sbit PT2 = IP^5;
#endif
#ifdef UART1_ENABLED
sbit PS1 = IP^6;
#endif
/* SCON1 */
#ifdef UART1_ENABLED
sbit RI1 = SCON1^0;
sbit TI1 = SCON1^1;
sbit RB18 = SCON1^2;
sbit TB18 = SCON1^3;
sbit REN1 = SCON1^4;
sbit SM12 = SCON1^5;
sbit SM11 = SCON1^6;
sbit SM10 = SCON1^7;
#endif
/* T2CON */
#ifdef CC_ENABLED
sbit T2I0 = T2CON^0;
sbit T2I1 = T2CON^1;
sbit T2CM = T2CON^2;
sbit T2R0 = T2CON^3;
sbit T2R1 = T2CON^4;
/* T2CON^5;*/
sbit I3FR = T2CON^6;
sbit T2PS = T2CON^7;
#else
#ifdef TIMER2_ENABLED
sbit CPRL2 = T2CON^0;
sbit CT2 = T2CON^1;
sbit TR2 = T2CON^2;
sbit EXEN2 = T2CON^3;
sbit TCLK = T2CON^4;
sbit RCLK = T2CON^5;
sbit EXF2 = T2CON^6;
sbit TF2 = T2CON^7;
#endif
#endif
/* PSW */
sbit P = PSW^0;
sbit F1 = PSW^1;
sbit OV = PSW^2;
sbit RS0 = PSW^3;
sbit RS1 = PSW^4;
sbit F0 = PSW^5;
sbit AC = PSW^6;
sbit CY = PSW^7;
/* WDCON */
#ifdef WATCHDOG_ENABLED
sbit RWT = WDCON^0;
sbit EWT = WDCON^1;
sbit WTRF = WDCON^2;
sbit WDIF = WDCON^3;
sbit INT5F = WDCON^4;
sbit INT6F = WDCON^5;
sbit INT7F = WDCON^6;
sbit INT8F = WDCON^7;
#endif
/* EIE */
sbit EX2 = EIE^0;
sbit EX3 = EIE^1;
sbit EX4 = EIE^2;
sbit EX5 = EIE^3;
sbit EX6 = EIE^4;
#ifdef WATCHDOG_ENABLED
sbit EWDI = EIE^5;
#endif
#ifdef DI2CM_ENABLED
sbit EI2CM = EIE^6;
#endif
#ifdef DI2CS_ENABLED
sbit EI2CS = EIE^7;
#endif
/* EIP */
sbit PX2 = EIP^0;
sbit PX3 = EIP^1;
sbit PX4 = EIP^2;
sbit PX5 = EIP^3;
sbit PX6 = EIP^4;
#ifdef WATCHDOG_ENABLED
sbit PWDI = EIP^5;
#endif
#ifdef DI2CM_ENABLED
sbit PI2CM = EIP^6;
#endif
#ifdef DI2CS_ENABLED
sbit PI2CS = EIP^7;
#endif
/*-------------------------------------------------------------------------
BIT Values
-------------------------------------------------------------------------*/
/* TMOD Bit Values */
#define T0_M0_ 0x01
#define T0_M1_ 0x02
#define T0_CT_ 0x04
#define T0_GATE_ 0x08
#define T1_M0_ 0x10
#define T1_M1_ 0x20
#define T1_CT_ 0x40
#define T1_GATE_ 0x80
/* CKCON Bit Values */
#define MD_ 0x07
#define T0M_ 0x08
#define T1M_ 0x10
#define T2M_ 0x20
#define WD_ 0xC0
/* EIF Bit Values */
#define INT2F_ 0x01
#define INT3F_ 0x02
#define INT4F_ 0x04
#define INT5F_ 0x08
#define INT6F_ 0x10
#ifdef DI2CM_ENABLED
#define I2CMIF_ 0x40
#endif
#ifdef DI2CS_ENABLED
#define I2CSIF_ 0x80
#endif
/* T2IF Bit Values */
#ifdef CC_ENABLED
#define T2_TF2_ 0x01
#define T2_EXF2_ 0x02
#define T2_EXEN2_ 0x04
#endif
/* CCEN Bit Values */
#ifdef CC_ENABLED
#define T2_CM0_ 0x03
#define T2_CM1_ 0x0C
#define T2_CM2_ 0x30
#define T2_CM3_ 0xC0
#endif
#ifdef DSPI_ENABLED
/* DSPI Control bits */
#define SPCR_SPIE_ 0x80 /* Interrupt enable */
#define SPCR_SPE_ 0x40 /* SPI Enable */
#define SPCR_MSTR_ 0x10 /* Master(1)/Slave(0) */
#define SPCR_CPOL_ 0x08 /* Clock polarity Low(1)/High(0) */
#define SPCR_CPHA_ 0x04 /* Clock phase */
#define SPCR_SPR_ 0x23 /* Clock rate mask */
#define SPR(x) ((x&0x03)| ((x<<3)&0x20) )
#define DIV_BY_4 0x0
#define DIV_BY_8 0x1
#define DIV_BY_16 0x2
#define DIV_BY_32 0x3
#define DIV_BY_64 0x4
#define DIV_BY_128 0x5
#define DIV_BY_256 0x6
#define DIV_BY_512 0x7
/* DSPI Status bits */
#define SPSR_SPIF_ 0x80 /* Interrupt */
#define SPSR_WCOL_ 0x40 /* Write colision */
#define SPSR_MODF_ 0x10 /* Model fault */
/* DSPI Select Codes For SSCR register */
#define SEL_7 0x80
#define SEL_6 0x40
#define SEL_5 0x20
#define SEL_4 0x10
#define SEL_3 0x08
#define SEL_2 0x04
#define SEL_1 0x02
#define SEL_0 0x01
#endif
#ifdef DI2CS_ENABLED
/* DI2CS Status bits */
#define SR_TREQ 0x02
#define SR_RREQ 0x01
/*
DI2CS CODES written into control register I2CSCR to perfrom an action
Naming rules
<actual state of DI2CS>_<next code>_<RS_value>
*/
/* DI2CS in IDLE */
#define IDLE_START_SEND_0 0x03 /* RS=0 */
#define IDLE_START_SEND_STOP_0 0x07 /* RS=0 */
#define IDLE_START_RECEIVE_nACK_1 0x03 /* RS=1 */
#define IDLE_START_RECEIVE_STOP_1 0x07 /* RS=1 */
#define IDLE_START_RECEIVE_1 0x0B /* RS=1 */
#define IDLE_MASTERCODE_HS_0 0x11 /* RS=0 */
/* DI2CS in TRANSMIT */
#define TRANSMIT_SEND_x 0x01 /* RS=x */
#define TRANSMIT_STOP_x 0x04 /* RS=x */
#define TRANSMIT_SEND_STOP_x 0x05 /* RS=x */
#define TRANSMIT_START_SEND_0 0x03 /* RS=0 */
#define TRANSMIT_START_SEND_STOP_0 0x07 /* RS=0 */
#define TRANSMIT_START_RECEIVE_nACK_1 0x03 /* RS=1 */
#define TRANSMIT_START_SEND_STOP_1 0x07 /* RS=1 */
#define TRANSMIT_START_RECEIVE_1 0x0B /* RS=1 */
/* DI2CS in RECEIVE */
#define RECEIVE_RECEIVE_nACK_x 0x01 /* RS=x */
#define RECEIVE_STOP_x 0x04 /* RS=x */
#define RECEIVE_RECEIVE_STOP_x 0x05 /* RS=x */
#define RECEIVE_RECEIVE_x 0x09 /* RS=x */
#define RECEIVE_START_RECEIVE_nACK_1 0x03 /* RS=1 */
#define RECEIVE_START_RECEIVE_STOP_1 0x07 /* RS=1 */
#define RECEIVE_START_RECEIVE_1 0x0B /* RS=1 */
#define RECEIVE_START_SEND_0 0x03 /* RS=0 */
#define RECEIVE_START_SEND_STOP_0 0x07 /* RS=0 */
#endif
#ifdef DI2CM_ENABLED
#define RS_1 0x01
#define RS_0 0xFE
/* DI2CM Status bits */
#define SR_BUS_BUSY 0x40
#define SR_IDLE 0x20
#define SR_ARB_LOST 0x10
#define SR_DATA_ACK 0x08
#define SR_ADDR_ACK 0x04
#define SR_ERROR 0x02
#define SR_BUSY 0x01
/*
DI2CM CODES written into control register I2CMCR to perfrom
an action. Naming rules
<actual state of DI2CM>_<next code>_<RS_value>
*/
/* DI2CM in IDLE state */
#define IDLE_START_SEND_0 0x03 /* RS=0 */
#define IDLE_START_SEND_STOP_0 0x07 /* RS=0 */
#define IDLE_START_RECEIVE_nACK_1 0x03 /* RS=1 */
#define IDLE_START_RECEIVE_STOP_1 0x07 /* RS=1 */
#define IDLE_START_RECEIVE_1 0x0B /* RS=1 */
#define IDLE_MASTERCODE_HS_x 0x11 /* RS=x */
/* DI2CM in TRANSMIT state */
#define TRANSMIT_SEND_x 0x01 /* RS=x */
#define TRANSMIT_STOP_x 0x04 /* RS=x */
#define TRANSMIT_SEND_STOP_x 0x05 /* RS=x */
#define TRANSMIT_START_SEND_0 0x03 /* RS=0 */
#define TRANSMIT_START_SEND_STOP_0 0x07 /* RS=0 */
#define TRANSMIT_START_RECEIVE_nACK_1 0x03 /* RS=1 */
#define TRANSMIT_START_SEND_STOP_1 0x07 /* RS=1 */
#define TRANSMIT_START_RECEIVE_1 0x0B /* RS=1 */
/* DI2CM in RECEIVE state */
#define RECEIVE_RECEIVE_nACK_x 0x01 /* RS=x */
#define RECEIVE_STOP_x 0x04 /* RS=x */
#define RECEIVE_RECEIVE_STOP_x 0x05 /* RS=x */
#define RECEIVE_RECEIVE_x 0x09 /* RS=x */
#define RECEIVE_START_RECEIVE_nACK_1 0x03 /* RS=1 */
#define RECEIVE_START_RECEIVE_STOP_1 0x07 /* RS=1 */
#define RECEIVE_START_RECEIVE_1 0x0B /* RS=1 */
#define RECEIVE_START_SEND_0 0x03 /* RS=0 */
#define RECEIVE_START_SEND_STOP_0 0x07 /* RS=0 */
#endif
#endif /*_DR80390XP_H_*/
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