upsd3400.h

Keil uVision2

/*  UPSD 3400 Extensions    */
/* ------------------------ */
DEFINE_SFR(P4,0xC0)         // New port 4
DEFINE_SFR(P1SFS0,0x8E)	    // Port 1 I/O select Register 0
DEFINE_SFR(P1SFS1,0x8F)	    // Port 1 I/O select Register 1
DEFINE_SFR(P3SFS,0x91)      // Port 3 I/O select
DEFINE_SFR(P4SFS0,0x92)     // Port 4 I/O select Register 0
DEFINE_SFR(P4SFS1,0x93)     // Port 4 I/O select Register 1

// --- ADC SFRs ---
DEFINE_SFR(ADCPS,0x94)      // ADC Clock Control Register
DEFINE_SFR(ADAT0,0x95)      // ADC Data Register1 ADAT[9:8]
DEFINE_SFR(ADAT1,0x96)      // ADC Data Register0 ADAT[7:0]
DEFINE_SFR(ACON,0x97)       // ADC Control Register

// --- UART1 SFRS ----
DEFINE_SFR(SCLK1,0xD1)      // UART1 Rx/Tx Clock
DEFINE_SFR(SCON1,0xD8)      // UART1 Serial Control
DEFINE_SFR(SBUF1,0xD9)      // UART1 Serial Buffer

// --- PCA SFRs ------
DEFINE_SFR(PCACL0,0xA2)     // PCA0 Counter Low
DEFINE_SFR(PCACH0,0xA3)     // PCA0 Counter High
DEFINE_SFR(PCACON0,0xA4)    // PCA0 Configuration Register
DEFINE_SFR(PCASTA,0xA5)     // PCA0, PCA1 Status Register
DEFINE_SFR(PCACL1,0xBA)     // PCA1 Counter Low
DEFINE_SFR(PCACH1,0xBB)     // PCA1 Counter High
DEFINE_SFR(PCACON1,0xBC)    // PCA1 Configuration Register 
DEFINE_SFR(PWMF0,0xB4)      // PCA0 PWM Frequency
DEFINE_SFR(PWMF1,0xC7)      // PCA1 PWM Frequency

// ---TCM SFRs -------
DEFINE_SFR(TCMMODE0,0xA9)   // TCM0 Mode Register   
DEFINE_SFR(TCMMODE1,0xAA)   // TCM1 Mode Register   
DEFINE_SFR(TCMMODE2,0xAB)   // TCM2 Mode Register
DEFINE_SFR(TCMMODE3,0xBD)   // TCM3 Mode Register
DEFINE_SFR(TCMMODE4,0xBE)   // TCM4 Mode Register
DEFINE_SFR(TCMMODE5,0xBF)   // TCM5 Mode Register
DEFINE_SFR(CAPCOML0,0xAC)   // TCM0 Capture/Compare Register Low  
DEFINE_SFR(CAPCOMH0,0xAD)   // TCM0 Capture/Compare Register High  
DEFINE_SFR(CAPCOML1,0xAF)   // TCM1 Capture/Compare Register Low  
DEFINE_SFR(CAPCOMH1,0xB1)   // TCM1 Capture/Compare Register High  
DEFINE_SFR(CAPCOML2,0xB2)   // TCM2 Capture/Compare Register Low  
DEFINE_SFR(CAPCOMH2,0xB3)   // TCM2 Capture/Compare Register High 
DEFINE_SFR(CAPCOML3,0xC1)   // TCM3 Capture/Compare Register Low  
DEFINE_SFR(CAPCOMH3,0xC2)   // TCM3 Capture/Compare Register High 
DEFINE_SFR(CAPCOML4,0xC3)   // TCM4 Capture/Compare Register Low  
DEFINE_SFR(CAPCOMH4,0xC4)   // TCM4 Capture/Compare Register High 
DEFINE_SFR(CAPCOML5,0xC5)   // TCM5 Capture/Compare Register Low  
DEFINE_SFR(CAPCOMH5,0xC6)   // TCM5 Capture/Compare Register High 

// --- WDT SFRs ---
DEFINE_SFR(WDRST,0xA6)      // Watch Dog Reset
DEFINE_SFR(WDKEY,0xAE)      // Watch Dog Key Enable

// --- INTERRUPT 2 SFRs ---
DEFINE_SFR(IEA,0xA7)        // Interrupt Enable (2nd)
DEFINE_SFR(IPA,0xB7)        // Interrupt Priority (2nd)

// --- I2C SFRs ---
DEFINE_SFR(S1SETUP,0xDB)    // I2C S1 Setup
DEFINE_SFR(S1CON,0xDC)      // I2C Bus Control Register
DEFINE_SFR(S1STA,0xDD)      // I2C Bus Status
DEFINE_SFR(S1DAT,0xDE)      // I2C Data Hold Register
DEFINE_SFR(S1ADR,0xDF)      // I2C Bus Address

// --- SPI SFRs ----
DEFINE_SFR(SPICLKD,0xD2)    // SPI Clock Divisor
DEFINE_SFR(SPISTAT,0xD3)    // SPI Status Reg.
DEFINE_SFR(SPITDR,0xD4)     // SPI Transmit Reg.
DEFINE_SFR(SPIRDR,0xD5)     // SPI Receive Reg.
DEFINE_SFR(SPICON0,0xD6)    // SPI Control0 Reg.
DEFINE_SFR(SPICON1,0xD7)    // SPI Control1 Reg.

// --- IrDA SFRs ----
DEFINE_SFR(IRDACON,0xCE)    // IrDA Configuration Register

// --- Clock Control SFRs ----
DEFINE_SFR(CCON0,0xF9)      // Debugger, CPU Clock Control
DEFINE_SFR(CCON1,0xFA)      // PLL Clock Control
DEFINE_SFR(CCON2,0xFB)      // PCA0 Clock Control
DEFINE_SFR(CCON3,0xFC)      // PCA1 Clock Control

// --- XDATA Pointer SFRs ----
DEFINE_SFR(DPTC,0x85)       // XData Pointer Control
DEFINE_SFR(DPTM,0x86)       // XData Pointer Mode

// --- Bus control SFRs -----
DEFINE_SFR(BUSCON,0x9D)     // Bus control

// --- USB SFRs -----
DEFINE_SFR(UADDR,0xE2)      // USB Address Register
DEFINE_SFR(UPAIR,0xE3)      // USB Pairing Control
DEFINE_SFR(UIE0,0xE4)       // USB Global Interrupt Enable
DEFINE_SFR(UIE1,0xE5)       // USB IN FIFO Interrupt Enable
DEFINE_SFR(UIE2,0xE6)       // USB OUT FIFO Interrupt Enable
DEFINE_SFR(UIE3,0xE7)       // USB IN FIFO NAK Interrupt Enable
DEFINE_SFR(UIF0,0xE8)       // USB Global Interrupt Flag
DEFINE_SFR(UIF1,0xE9)       // USB IN FIFO Interrupt Flag
DEFINE_SFR(UIF2,0xEA)       // USB OUT FIFO Inerrupt Flag
DEFINE_SFR(UIF3,0xEB)       // USB IN FIFO NAK Interrupt Flag
DEFINE_SFR(UCTL,0xEC)       // USB Control Register
DEFINE_SFR(USTA,0xED)       // USB Status
DEFINE_SFR(USEL,0xEF)       // USB Endpoint Control
DEFINE_SFR(UCON,0xF1)       // USB Endpoint Control
DEFINE_SFR(USIZE,0xF2)      // USB FIFO Valid Size
DEFINE_SFR(UBASEH,0xF3)     // USB Base Address Register High
DEFINE_SFR(UBASEL,0xF4)     // USB Base Address Register Low
DEFINE_SFR(USCI,0xF5)       // USB Setup Command Index
DEFINE_SFR(USCV,0xF6)       // USB Setup Command Value

/* --------------------------- */
/*  Common 8051 BIT Registers  */
/* --------------------------- */
/*  PSW  */
DEFINE_SFR_BIT(CY,PSW^7)
DEFINE_SFR_BIT(AC,PSW^6)
DEFINE_SFR_BIT(F0,PSW^5)
DEFINE_SFR_BIT(RS1,PSW^4)
DEFINE_SFR_BIT(RS0,PSW^3)
DEFINE_SFR_BIT(OV,PSW^2)
DEFINE_SFR_BIT(P,PSW^0) 	 

/*  TCON  */
DEFINE_SFR_BIT(TF1,TCON^7)   // Standard 8051 timer control
DEFINE_SFR_BIT(TR1,TCON^6)
DEFINE_SFR_BIT(TF0,TCON^5)
DEFINE_SFR_BIT(TR0,TCON^4)
DEFINE_SFR_BIT(IE1,TCON^3)
DEFINE_SFR_BIT(IT1,TCON^2)
DEFINE_SFR_BIT(IE0,TCON^1)
DEFINE_SFR_BIT(IT0,TCON^0)

/*  IE  */
DEFINE_SFR_BIT(EA,IE^7)     // Enable All interrupts
DEFINE_SFR_BIT(EDB,IE^6)    // Enable Debug
DEFINE_SFR_BIT(ET2,IE^5)    // Timer 2
DEFINE_SFR_BIT(ES,IE^4)	    // Usart 0	
DEFINE_SFR_BIT(ES0,IE^4)    // Usart 0 (ES also known as ES0)	
DEFINE_SFR_BIT(ET1,IE^3)    // Timer 1
DEFINE_SFR_BIT(EX1,IE^2)    // External Int1
DEFINE_SFR_BIT(ET0,IE^1)    // Timer 0
DEFINE_SFR_BIT(EX0,IE^0)    // External Int0
           
/*  T2CON  */
DEFINE_SFR_BIT(TF2 ,T2CON^7)
DEFINE_SFR_BIT(EXF2,T2CON^6)
DEFINE_SFR_BIT(RCLK,T2CON^5)
DEFINE_SFR_BIT(TCLK,T2CON^4)
DEFINE_SFR_BIT(EXEN2,T2CON^3)
DEFINE_SFR_BIT(TR2,T2CON^2)
DEFINE_SFR_BIT(C_T2,T2CON^1)
DEFINE_SFR_BIT(CP_RL2,T2CON^0)

/*    P1 GPIO   */
DEFINE_SFR_BIT(P1_7,P1^7)   // bit 7 of P1
DEFINE_SFR_BIT(P1_6,P1^6)   // bit 6 of P1
DEFINE_SFR_BIT(P1_5,P1^5)   // bit 5 of P1
DEFINE_SFR_BIT(P1_4,P1^4)   // bit 4 of P1
DEFINE_SFR_BIT(P1_3,P1^3)   // bit 3 of P1
DEFINE_SFR_BIT(P1_2,P1^2)   // bit 2 of P1
DEFINE_SFR_BIT(P1_1,P1^1)   // bit 1 of P1
DEFINE_SFR_BIT(P1_0,P1^0)   // bit 0 of P1

/*    P3 GPIO   */
DEFINE_SFR_BIT(P3_7,P3^7)   // bit 7 of P3
DEFINE_SFR_BIT(P3_6,P3^6)   // bit 6 of P3
DEFINE_SFR_BIT(P3_5,P3^5)   // bit 5 of P3
DEFINE_SFR_BIT(P3_4,P3^4)   // bit 4 of P3
DEFINE_SFR_BIT(P3_3,P3^3)   // bit 3 of P3
DEFINE_SFR_BIT(P3_2,P3^2)   // bit 2 of P3
DEFINE_SFR_BIT(P3_1,P3^1)   // bit 1 of P3
DEFINE_SFR_BIT(P3_0,P3^0)   // bit 0 of P3

/*    P4 GPIO   */
DEFINE_SFR_BIT(P4_7,P4^7)   // bit 7 of P4
DEFINE_SFR_BIT(P4_6,P4^6)   // bit 6 of P4
DEFINE_SFR_BIT(P4_5,P4^5)   // bit 5 of P4
DEFINE_SFR_BIT(P4_4,P4^4)   // bit 4 of P4
DEFINE_SFR_BIT(P4_3,P4^3)   // bit 3 of P4
DEFINE_SFR_BIT(P4_2,P4^2)   // bit 2 of P4
DEFINE_SFR_BIT(P4_1,P4^1)   // bit 1 of P4
DEFINE_SFR_BIT(P4_0,P4^0)   // bit 0 of P4

/*  SCON1   */
DEFINE_SFR_BIT(SM01,SCON1^7)
DEFINE_SFR_BIT(SM11,SCON1^6)
DEFINE_SFR_BIT(SM21,SCON1^5)
DEFINE_SFR_BIT(REN1,SCON1^4)
DEFINE_SFR_BIT(TB81,SCON1^3)
DEFINE_SFR_BIT(RB81,SCON1^2)
DEFINE_SFR_BIT(TI1,SCON1^1)
DEFINE_SFR_BIT(RI1,SCON1^0)

/*  IP  */
DEFINE_SFR_BIT(PDB,IP^6)    // Debug
DEFINE_SFR_BIT(PT2,IP^5)    // Timer 2
DEFINE_SFR_BIT(PS,IP^4)     // Usart 0
DEFINE_SFR_BIT(PS0,IP^4)    // Usart 0 (PS also known as PS0)
DEFINE_SFR_BIT(PT1,IP^3)    // Timer 1
DEFINE_SFR_BIT(PX1,IP^2)    // Ext Int1
DEFINE_SFR_BIT(PT0,IP^1)    // Timer 0
DEFINE_SFR_BIT(PX0,IP^0)    // Ext Int 0

/*  SCON  (SCON0) */
DEFINE_SFR_BIT(SM0,SCON^7)  // Standard 8051 Uart Control
DEFINE_SFR_BIT(SM1,SCON^6)
DEFINE_SFR_BIT(SM2,SCON^5)
DEFINE_SFR_BIT(REN,SCON^4)
DEFINE_SFR_BIT(TB8,SCON^3)
DEFINE_SFR_BIT(RB8,SCON^2)
DEFINE_SFR_BIT(TI,SCON^1)
DEFINE_SFR_BIT(RI,SCON^0)

/*  UIF0 */                     // USB Global Interrupt Flags
DEFINE_SFR_BIT(GLF,UIF0^7)      // Global USB Interrupt Flag
DEFINE_SFR_BIT(INF,UIF0^6)      // IN FIFO Interrupt Flag
DEFINE_SFR_BIT(OUTF,UIF0^5)     // OUT FIFO Interrupt Flag
DEFINE_SFR_BIT(NAKF,UIF0^4)     // NAK Interrupt Flag
DEFINE_SFR_BIT(RSTF,UIF0^3)     // USB Reset Interrupt Flag
DEFINE_SFR_BIT(SUSPNDF,UIF0^2)  // USB Suspend Mode Interrupt Flag
DEFINE_SFR_BIT(EOPF,UIF0^1)     // End of Packet Interrupt Flag
DEFINE_SFR_BIT(RESUMF,UIF0^0)   // Resume Interrupt Flag


/* -----------------------------------
Interrupt Vectors:
Interrupt Address = (Number * 8) + 3
------------------------------------ */ 
#define RESET_VECTOR_ADDR               0          // Reset Address = 0
#define IE0_VECTOR              0                  //0x03 External Interrupt 0
#define IE0_VECTOR_ADDR                 0x03
#define TF0_VECTOR              1                  //0x0B Timer 0
#define TF0_VECTOR_ADDR                 0x0B
#define IE1_VECTOR              2                  //0x13 External Interrupt 1
#define IE1_VECTOR_ADDR                 0x13
#define TF1_VECTOR              3                  //0x1B Timer 1
#define TF1_VECTOR_ADDR                 0x1B
#define UART0_VECTOR            4                  //0x23 Serial Port 0
#define UART0_VECTOR_ADDR               0x23
#define TF2_VECTOR              5                  //0x2B Timer 2
#define TF2_VECTOR_ADDR                 0x2B
#define USB_VECTOR              6                  //0x33 USB
#define USB_VECTOR_ADDR                 0x33
#define ADC_VECTOR              7                  //0x3B ADC
#define ADC_VECTOR_ADDR                 0x3B
#define I2C_VECTOR              8                  //0x43 I2C
#define I2C_VECTOR_ADDR                 0x43	
#define UART1_VECTOR            9                  //0x4B Serial Port 1
#define UART1_VECTOR_ADDR               0x4B	
#define SPI_VECTOR             10                  //0x53 SPI
#define SPI_VECTOR_ADDR                 0x53
#define PCA_VECTOR             11                  //0x5B PCA
#define PCA_VECTOR_ADDR                 0x5B
#define DBG_VECTOR             12                  //0x63 DEBUG (Highest Priority)
#define DBG_VECTOR_ADDR                 0x63
/* ---------------------------------- */

#endif