smallcore.map.eqn

嵌入式系统实验教程(一)中对应的实验内容

--G1L845 is nios2e_1C6:inst|cpu:the_cpu|add~1610
--operation mode is arithmetic

G1L845 = AMPP_FUNCTION(G1_F_pc[9], G1L115);

--G1L945 is nios2e_1C6:inst|cpu:the_cpu|add~1612
--operation mode is arithmetic

G1L945 = AMPP_FUNCTION(G1_F_pc[9], G1L115);


--G1L055 is nios2e_1C6:inst|cpu:the_cpu|add~1615
--operation mode is arithmetic

G1L055 = AMPP_FUNCTION(G1_E_src2[18], G1_E_src1[18], G1L345);

--G1L155 is nios2e_1C6:inst|cpu:the_cpu|add~1617
--operation mode is arithmetic

G1L155 = AMPP_FUNCTION(G1_E_src2[18], G1_E_src1[18], G1L345);


--G1L255 is nios2e_1C6:inst|cpu:the_cpu|add~1620
--operation mode is arithmetic

G1L255 = AMPP_FUNCTION(G1_E_src2[18], G1_E_src1[18], G1L545);

--G1L355 is nios2e_1C6:inst|cpu:the_cpu|add~1622
--operation mode is arithmetic

G1L355 = AMPP_FUNCTION(G1_E_src2[18], G1_E_src1[18], G1L545);


--G1L455 is nios2e_1C6:inst|cpu:the_cpu|add~1625
--operation mode is arithmetic

G1L455 = AMPP_FUNCTION(G1_F_pc[16], G1L745);

--G1L555 is nios2e_1C6:inst|cpu:the_cpu|add~1627
--operation mode is arithmetic

G1L555 = AMPP_FUNCTION(G1_F_pc[16], G1L745);


--G1L655 is nios2e_1C6:inst|cpu:the_cpu|add~1630
--operation mode is arithmetic

G1L655 = AMPP_FUNCTION(G1_E_src2[21], G1_E_src1[21], G1L775);

--G1L755 is nios2e_1C6:inst|cpu:the_cpu|add~1632
--operation mode is arithmetic

G1L755 = AMPP_FUNCTION(G1_E_src2[21], G1_E_src1[21], G1L775);


--G1L855 is nios2e_1C6:inst|cpu:the_cpu|add~1635
--operation mode is arithmetic

G1L855 = AMPP_FUNCTION(G1_E_src2[21], G1_E_src1[21], G1L975);

--G1L955 is nios2e_1C6:inst|cpu:the_cpu|add~1637
--operation mode is arithmetic

G1L955 = AMPP_FUNCTION(G1_E_src2[21], G1_E_src1[21], G1L975);


--G1L065 is nios2e_1C6:inst|cpu:the_cpu|add~1640
--operation mode is arithmetic

G1L065 = AMPP_FUNCTION(G1_F_pc[19], G1L185);

--G1L165 is nios2e_1C6:inst|cpu:the_cpu|add~1642
--operation mode is arithmetic

G1L165 = AMPP_FUNCTION(G1_F_pc[19], G1L185);


--G1L265 is nios2e_1C6:inst|cpu:the_cpu|add~1645
--operation mode is arithmetic

G1L265 = AMPP_FUNCTION(G1_F_pc[20], G1L165);

--G1L365 is nios2e_1C6:inst|cpu:the_cpu|add~1647
--operation mode is arithmetic

G1L365 = AMPP_FUNCTION(G1_F_pc[20], G1L165);


--G1L465 is nios2e_1C6:inst|cpu:the_cpu|add~1650
--operation mode is arithmetic

G1L465 = AMPP_FUNCTION(G1_E_src2[13], G1_E_src1[13], G1L135);

--G1L565 is nios2e_1C6:inst|cpu:the_cpu|add~1652
--operation mode is arithmetic

G1L565 = AMPP_FUNCTION(G1_E_src2[13], G1_E_src1[13], G1L135);


--G1L665 is nios2e_1C6:inst|cpu:the_cpu|add~1655
--operation mode is arithmetic

G1L665 = AMPP_FUNCTION(G1_E_src2[13], G1_E_src1[13], G1L335);

--G1L765 is nios2e_1C6:inst|cpu:the_cpu|add~1657
--operation mode is arithmetic

G1L765 = AMPP_FUNCTION(G1_E_src2[13], G1_E_src1[13], G1L335);


--G1L865 is nios2e_1C6:inst|cpu:the_cpu|add~1660
--operation mode is arithmetic

G1L865 = AMPP_FUNCTION(G1_F_pc[11], G1L535);

--G1L965 is nios2e_1C6:inst|cpu:the_cpu|add~1662
--operation mode is arithmetic

G1L965 = AMPP_FUNCTION(G1_F_pc[11], G1L535);


--G1L075 is nios2e_1C6:inst|cpu:the_cpu|add~1665
--operation mode is arithmetic

G1L075 = AMPP_FUNCTION(G1_E_src2[19], G1_E_src1[19], G1L155);

--G1L175 is nios2e_1C6:inst|cpu:the_cpu|add~1667
--operation mode is arithmetic

G1L175 = AMPP_FUNCTION(G1_E_src2[19], G1_E_src1[19], G1L155);


--G1L275 is nios2e_1C6:inst|cpu:the_cpu|add~1670
--operation mode is arithmetic

G1L275 = AMPP_FUNCTION(G1_E_src2[19], G1_E_src1[19], G1L355);

--G1L375 is nios2e_1C6:inst|cpu:the_cpu|add~1672
--operation mode is arithmetic

G1L375 = AMPP_FUNCTION(G1_E_src2[19], G1_E_src1[19], G1L355);


--G1L475 is nios2e_1C6:inst|cpu:the_cpu|add~1675
--operation mode is arithmetic

G1L475 = AMPP_FUNCTION(G1_F_pc[17], G1L555);

--G1L575 is nios2e_1C6:inst|cpu:the_cpu|add~1677
--operation mode is arithmetic

G1L575 = AMPP_FUNCTION(G1_F_pc[17], G1L555);


--G1L675 is nios2e_1C6:inst|cpu:the_cpu|add~1680
--operation mode is arithmetic

G1L675 = AMPP_FUNCTION(G1_E_src2[20], G1_E_src1[20], G1L175);

--G1L775 is nios2e_1C6:inst|cpu:the_cpu|add~1682
--operation mode is arithmetic

G1L775 = AMPP_FUNCTION(G1_E_src2[20], G1_E_src1[20], G1L175);


--G1L875 is nios2e_1C6:inst|cpu:the_cpu|add~1685
--operation mode is arithmetic

G1L875 = AMPP_FUNCTION(G1_E_src2[20], G1_E_src1[20], G1L375);

--G1L975 is nios2e_1C6:inst|cpu:the_cpu|add~1687
--operation mode is arithmetic

G1L975 = AMPP_FUNCTION(G1_E_src2[20], G1_E_src1[20], G1L375);


--G1L085 is nios2e_1C6:inst|cpu:the_cpu|add~1690
--operation mode is arithmetic

G1L085 = AMPP_FUNCTION(G1_F_pc[18], G1L575);

--G1L185 is nios2e_1C6:inst|cpu:the_cpu|add~1692
--operation mode is arithmetic

G1L185 = AMPP_FUNCTION(G1_F_pc[18], G1L575);


--RC1_safe_q[9] is delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[9]
--operation mode is arithmetic

RC1_safe_q[9]_carry_eqn = RC1L81;
RC1_safe_q[9]_lut_out = RC1_safe_q[9] $ (!RC1_cout & RC1_safe_q[9]_carry_eqn);
RC1_safe_q[9] = DFFEAS(RC1_safe_q[9]_lut_out, SYS_CLK2, SYS_nRST, , , , , , );

--RC1L02 is delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|counter_cella9~COUT
--operation mode is arithmetic

RC1L02 = CARRY(!RC1L81 # !RC1_safe_q[9]);


--AB1_q_a[23] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[23]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[23] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[23], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[7], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);

--AB1_q_b[23] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_b[23]
AB1_q_b[23] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[23], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[7], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);


--G1_E_shift_rot_result[24] is nios2e_1C6:inst|cpu:the_cpu|E_shift_rot_result[24]
--operation mode is normal

G1_E_shift_rot_result[24] = AMPP_FUNCTION(NC1__clk0, G1_E_shift_rot_result[23], G1_E_shift_rot_result[25], G1_E_src1[24], G1_R_ctrl_shift_rot_right, F1_data_out, G1_E_new_inst);


--AB1_q_a[21] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[21]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[21] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[21], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[5], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);

--AB1_q_b[21] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_b[21]
AB1_q_b[21] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[21], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[5], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);


--AB1_q_a[20] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[20]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[20] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[20], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[4], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);

--AB1_q_b[20] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_b[20]
AB1_q_b[20] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[20], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[4], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);


--AB1_q_a[19] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[19]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[19] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[19], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[3], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);

--AB1_q_b[19] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_b[19]
AB1_q_b[19] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[19], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[3], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);


--AB1_q_a[18] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[18]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[18] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[18], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[2], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);

--AB1_q_b[18] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_b[18]
AB1_q_b[18] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[18], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[2], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);


--AB1_q_a[17] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[17]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[17] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[17], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[1], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);

--AB1_q_b[17] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_b[17]
AB1_q_b[17] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[17], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[1], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);


--AB1_q_a[16] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[16]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[16] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[16], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[0], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);

--AB1_q_b[16] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_b[16]
AB1_q_b[16] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[16], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte2_data[0], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);


--AB1_q_a[15] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[15]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[15] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[15], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte1_data[7], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);

--AB1_q_b[15] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_b[15]
AB1_q_b[15] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[15], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte1_data[7], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);


--AB1_q_a[13] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[13] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[13], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte1_data[5], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);

--AB1_q_b[13] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_b[13]
AB1_q_b[13] = AMPP_FUNCTION(G1_W_rf_wren_a, G1L837, NC1__clk0, NC1__clk0, G1_W_alu_result[13], G1L937, G1L047, G1L147, G1L247, G1L347, G1_av_ld_byte1_data[5], G1_D_iw[22], G1_D_iw[23], G1_D_iw[24], G1_D_iw[25], G1_D_iw[26]);


--AB1_q_a[12] is nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_dno1:auto_generated|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
AB1_q_a[12] = AMPP_FUNCTION(G1_