smallcore.map.rpt

嵌入式系统实验教程(一)中对应的实验内容

Analysis & Synthesis report for SmallCore
Wed Aug 16 18:02:05 2006
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Parameter Settings for User Entity Instance: pll:inst1|altpll:altpll_component
  6. Parameter Settings for User Entity Instance: nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf
  7. Parameter Settings for User Entity Instance: nios2e_1C6:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram
  8. Parameter Settings for User Entity Instance: nios2e_1C6:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
  9. Parameter Settings for User Entity Instance: nios2e_1C6:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 10. Parameter Settings for User Entity Instance: nios2e_1C6:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component
 11. Parameter Settings for User Entity Instance: nios2e_1C6:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 12. Parameter Settings for User Entity Instance: nios2e_1C6:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1
 13. Parameter Settings for User Entity Instance: nios2e_1C6:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
 14. Parameter Settings for User Entity Instance: nios2e_1C6:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
 15. Parameter Settings for User Entity Instance: nios2e_1C6:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
 16. Parameter Settings for User Entity Instance: delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component
 17. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 18. Multiplexer Restructuring Statistics (Restructuring Performed)
 19. Registers Protected by SYN_PRESERVE, DONT_TOUCH
 20. State Machine - |SmallCore|nios2e_1C6:inst|sdram:the_sdram|i_state
 21. State Machine - |SmallCore|nios2e_1C6:inst|sdram:the_sdram|i_next
 22. State Machine - |SmallCore|nios2e_1C6:inst|sdram:the_sdram|m_state
 23. State Machine - |SmallCore|nios2e_1C6:inst|sdram:the_sdram|m_next
 24. State Machine - |SmallCore|nios2e_1C6:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize
 25. Partition for Top-Level Resource Utilization by Entity
 26. Analysis & Synthesis Equations
 27. Multiplexer Restructuring Statistics (Restructuring Performed)
 28. Partition "sld_hub:sld_hub_inst" Resource Utilization by Entity
 29. Analysis & Synthesis Equations
 30. scfifo Parameter Settings by Entity Instance
 31. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Aug 16 18:02:05 2006         ;
; Quartus II Version          ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name               ; SmallCore                                     ;
; Top-level Entity Name       ; SmallCore                                     ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; N/A until Partition Merge                     ;
; Total pins                  ; N/A until Partition Merge                     ;
; Total virtual pins          ; N/A until Partition Merge                     ;
; Total memory bits           ; N/A until Partition Merge                     ;
; Total PLLs                  ; N/A until Partition Merge                     ;
+-----------------------------+-----------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C6Q240C8  ;               ;
; Top-level entity name                                              ; SmallCore    ; SmallCore     ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Use smart compilation                                              ; Off          ; Off           ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;
; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced     ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70           ; 70            ;
; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;
; Auto Clock Enable Replacement                                      ; On           ; On            ;