📄 drvcpu.c
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////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006-2007 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (¨MStar Confidential Information〃) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
// Description: CPU setting Module
//
///////////////////////////////////////////////////////////////////////////////
#define DRVCPU_C
#include <intrins.h>
#include <string.h>
#include "R8051XC.h"
#include "datatype.h"
#include "hwreg.h"
#include "Board.h"
#include "sysinfo.h"
#include "drvserflash_db.h"
#include "drvsys.h"
#include "Bin_ID.h"
#include "drvmiu.h"
#include "drvcpu.h"
#include "drvGlobal.h"
#include "panel.h"
#include "drvtimer.h"
#define CPU_DEBUGINFO(x) x
void MDrv_Change_CPU_Speed(U8 type)
{
U8 u8Value;
DWORD u32Value;
CPU_DEBUGINFO(printf("\r\n Change MCU Speed:%bu\n", type));
CPU_DEBUGINFO(printf("REL:0x%08LX, TH1:0x%08LX\n", UART_BAUDRATE_CLKREL, UART_BAUDRATE_CLK));
// seven 070821
//#ifdef MOSES // kevin c
// #if (MST_XTAL_CLOCK_HZ == FREQ_14P318MHZ)// kevin e
// XBYTE[0x2514]=0x0F; // 14.318MHz - > 216MHz ()
// #elif (MST_XTAL_CLOCK_HZ == FREQ_12MHZ)
// XBYTE[0x2514]=0x12; // 12MHz - > 216MHz ()
// #else
// #error "Wrong Divider setting A"
// #endif
//#endif
// end
// Switch back to XTAL for protect high speed switch
XBYTE[REG_CT_MISC0] &= ~MISC_MCU_CLKSEL_MASK;
// Read original setting
u8Value = XBYTE[REG_CKG_MCU] & ~MCU_CLK_MASK;
XBYTE[PLL_CONTROL_IN_ATOP] &= ~BIT7; //select mpll post divider; 0=div3; 1=div2.5;
#define MCU_CLOCK (MCU_CLOCK_SEL == MCUCLK_XTAL ? MCU_CLOCK_BOOT : \
MCU_CLOCK_SEL == MCUCLK_54MHZ ? FREQ_54MHZ : \
MCU_CLOCK_SEL == MCUCLK_144MHZ ? FREQ_144MHZ : \
MCU_CLOCK_SEL == MCUCLK_123MHZ ? FREQ_123MHZ : \
MCU_CLOCK_SEL == MCUCLK_108MHZ ? FREQ_108MHZ : \
MCU_CLOCK_SEL == MCUCLK_86MHZ ? FREQ_86MHZ : \
MCU_CLOCK_SEL == MCUCLK_MEM ? MIU_CLOCK : \
MCU_CLOCK_SEL == MCUCLK_MEMD2 ? (MIU_CLOCK / 2) : \
MCU_CLOCK_BOOT)
// Programming new speed setting
switch (type)
{
case MCUCLK_54MHZ:
u8Value |= MCU_CLK_54MHZ;
u32Value = FREQ_54MHZ;
break;
case MCUCLK_144MHZ:
u8Value |= MCU_CLK_144MHZ;
u32Value = FREQ_144MHZ;
break;
case MCUCLK_123MHZ:
u8Value |= MCU_CLK_123MHZ;
u32Value = FREQ_123MHZ;
break;
case MCUCLK_108MHZ:
u8Value |= MCU_CLK_108MHZ;
u32Value = FREQ_108MHZ;
break;
case MCUCLK_86MHZ:
u8Value |= MCU_CLK_86MHZ;
u32Value = FREQ_86MHZ;
break;
case MCUCLK_MEM:
u8Value |= MCU_CLK_MEM;
u32Value = MIU_CLOCK;
break;
case MCUCLK_MEMD2:
u8Value |= MCU_CLK_MEMD2;
u32Value = (MIU_CLOCK / 2);
break;
default:
case MCUCLK_XTAL:
XBYTE[REG_CT_MISC0] &= ~MISC_MCU_CLKSEL_MASK;
u32Value = MCU_CLOCK_BOOT;
break;
}
XBYTE[REG_CKG_MCU] = u8Value;
// Select MCU clock XTAL or CKG
if (type != MCUCLK_XTAL)
XBYTE[REG_CT_MISC0] |= MISC_MCU_CLKSEL_EX;
/*//Change SPI speed kevin
XBYTE[0x3C4C] &= ~_BIT5;
XBYTE[0x3C4C] = (XBYTE[0x3C4C] & ~(_BIT4+_BIT3+_BIT2)) | (_BIT1 << 2);
XBYTE[0x3C4C] |= _BIT5;*/
//--------------------------------------------
// Update buadrate generators for MCU_CLOCK
//--------------------------------------------
if ( ENABLE_UART0 )
{
S0RELL = (UART_CLKREL(u32Value, UART0_BAUDRATE) & 0xff);
S0RELH = ((UART_CLKREL(u32Value, UART0_BAUDRATE) >> 8) & 0x3);
MDrv_Sys_SetInterrupt( SERIAL0, ENABLE_UART0_INTERRUPT );
}
if ( ENABLE_UART1 )
{
S1RELL = (UART_CLKREL(u32Value, UART1_BAUDRATE) & 0xff);
S1RELH = ((UART_CLKREL(u32Value, UART1_BAUDRATE) >> 8) & 0x3);
MDrv_Sys_SetInterrupt( SERIAL1, ENABLE_UART1_INTERRUPT );
}
#if USE_PIU_UART
MDrv_WriteRegBit(BK_PIU_MISC_14_H, 1, _BIT7);
MDrv_Write2Byte(BK_PIU_MISC_12_L, UART_FIFO_BAUDRATE(u32Value, UART0_BAUDRATE));
MDrv_WriteRegBit(BK_PIU_MISC_14_H, 0, _BIT7);
#endif
CPU_DEBUGINFO(printf("\r\n *** Change CPU Speed done ***")); // kevin test
}
//------------------------------------------------------------------------------
void MDrv_Change_SPI_Speed(U8 type)
{
U8 u8Value=XBYTE[BK_PIU_MISC_26_L]&0xC2;
XBYTE[BK_CHIPTOP_03_L]=0x3F;
XBYTE[BK_PIU_MISC_20_L]=0xFF;
XBYTE[BK_PIU_MISC_20_H]|=(_BIT7|0x0F);// flash fast read mode
// Programming new speed setting
switch (type)
{
case SPICLK_27MHZ:
u8Value |= SPI_CLK_27MHZ;
break;
case SPICLK_36MHZ:
u8Value |= SPI_CLK_36MHZ;
break;
case SPICLK_43MHZ:
u8Value |= SPI_CLK_43MHZ;
break;
case SPICLK_54MHZ:
u8Value |= SPI_CLK_54MHZ;
break;
case SPICLK_72MHZ:
u8Value |= SPI_CLK_72MHZ;
break;
case SPICLK_86MHZ:
u8Value |= SPI_CLK_108MHZ;
break;
default:
case SPICLK_XTAL:
break;
}
// disable icache , don't remove
MDrv_WriteRegBit(BK_2B_50_L,TRUE,_BIT0); // Enable cache pass mode
MDrv_WriteRegBit(BK_MCU_0C_L,FALSE,_BIT3); // Enable cache reset
XBYTE[BK_PIU_MISC_26_L]&=~_BIT5;
MDrv_Timer_Delayms(1); // don't remove
// Select SPI clock XTAL
// if (type != SPICLK_XTAL)
{
XBYTE[BK_PIU_MISC_26_L] = u8Value;
MDrv_Timer_Delayms(1); // don't remove
XBYTE[BK_PIU_MISC_26_L]|=_BIT5;
MDrv_Timer_Delayms(1); // don't remove
}
// enable icache , don't remove
MDrv_WriteRegBit(BK_MCU_0C_L,TRUE,_BIT3); // disable cache reset
MDrv_WriteRegBit(BK_2B_50_L,FALSE,_BIT0); // disable cache pass mode
CPU_DEBUGINFO(printf("\r\n Changed SPI Speed:%bu\n", type));
}
//------------------------------------------------------------------------------
void MDrv_Change_VD_Speed(U8 type)
{
U8 u8REG1E4C_L, u8REG1E17_L;
u8REG1E17_L = XBYTE[BK_CHIPTOP_17_L] & 0xF3;
u8REG1E4C_L = XBYTE[BK_CHIPTOP_4C_L] & 0xF3;
// Programming new speed setting
switch (type)
{
case VDMCU_CLOCK_54MHZ:
//u8REG1E2E &= ~VDMCU_CLK_108MHZ;
break;
case VDMCU_CLOCK_61MHZ:
u8REG1E17_L |= VDMCU_CLK_61MHZ;
break;
case VDMCU_CLOCK_30MHZ:
u8REG1E17_L |= VDMCU_CLK_30MHZ;
break;
case VDMCU_CLOCK_108MHZ:
u8REG1E17_L |= VDMCU_CLK_108MHZ;
break;
case VDMCU_CLOCK_86MHZ:
default:
u8REG1E4C_L |= _BIT2;
//u8REG1E2E &= ~VDMCU_CLK_36MHZ;
break;
case VDMCU_CLOCK_MEM:
u8REG1E4C_L |= _BIT2;
u8REG1E17_L |= VDMCU_CLK_MEM;
break;
case VDMCU_CLOCK_MEMDIV2:
u8REG1E4C_L |= _BIT2;
u8REG1E17_L |= VDMCU_CLK_MEMDIV2;
break;
case VDMCU_CLOCK_36MHZ:
u8REG1E4C_L |= _BIT2;
u8REG1E17_L |= VDMCU_CLK_36MHZ;
break;
}
XBYTE[BK_CHIPTOP_4C_L] = u8REG1E4C_L;
XBYTE[BK_CHIPTOP_17_L] = u8REG1E17_L;
XBYTE[BK_CHIPTOP_4C_L] |= _BIT3;
CPU_DEBUGINFO(printf("\r\n Changed VD Speed:%bu\n", type));
}
//------------------------------------------------------------------------------
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