led_test.hier_info

买的开发板上自带的例程

cpu_0_data_master_address_to_slave[8] <= cpu_0_data_master_address[8].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[9] <= cpu_0_data_master_address[9].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[10] <= cpu_0_data_master_address[10].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[11] <= cpu_0_data_master_address[11].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[12] <= cpu_0_data_master_address[12].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[13] <= cpu_0_data_master_address[13].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[0] <= cpu_0_data_master_readdata~192.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[1] <= cpu_0_data_master_readdata~193.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[2] <= cpu_0_data_master_readdata~194.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[3] <= cpu_0_data_master_readdata~195.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[4] <= cpu_0_data_master_readdata~196.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[5] <= cpu_0_data_master_readdata~197.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[6] <= cpu_0_data_master_readdata~198.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[7] <= cpu_0_data_master_readdata~199.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[8] <= cpu_0_data_master_readdata~200.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[9] <= cpu_0_data_master_readdata~201.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[10] <= cpu_0_data_master_readdata~202.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[11] <= cpu_0_data_master_readdata~203.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[12] <= cpu_0_data_master_readdata~204.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[13] <= cpu_0_data_master_readdata~205.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[14] <= cpu_0_data_master_readdata~206.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[15] <= cpu_0_data_master_readdata~207.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[16] <= cpu_0_data_master_readdata~208.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[17] <= cpu_0_data_master_readdata~209.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[18] <= cpu_0_data_master_readdata~210.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[19] <= cpu_0_data_master_readdata~211.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[20] <= cpu_0_data_master_readdata~212.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[21] <= cpu_0_data_master_readdata~213.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[22] <= cpu_0_data_master_readdata~214.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[23] <= cpu_0_data_master_readdata~215.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[24] <= cpu_0_data_master_readdata~216.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[25] <= cpu_0_data_master_readdata~217.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[26] <= cpu_0_data_master_readdata~218.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[27] <= cpu_0_data_master_readdata~219.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[28] <= cpu_0_data_master_readdata~220.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[29] <= cpu_0_data_master_readdata~221.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[30] <= cpu_0_data_master_readdata~222.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_readdata[31] <= cpu_0_data_master_readdata~223.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_waitrequest <= cpu_0_data_master_waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE


|led_test|first_nios2_system:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master
clk => cpu_0_instruction_master_read_but_no_slave_selected.CLK
clk => cpu_0_instruction_master_latency_counter~reg0.CLK
cpu_0_instruction_master_address[0] => cpu_0_instruction_master_address_to_slave[0].DATAIN
cpu_0_instruction_master_address[1] => cpu_0_instruction_master_address_to_slave[1].DATAIN
cpu_0_instruction_master_address[2] => cpu_0_instruction_master_address_to_slave[2].DATAIN
cpu_0_instruction_master_address[3] => cpu_0_instruction_master_address_to_slave[3].DATAIN
cpu_0_instruction_master_address[4] => cpu_0_instruction_master_address_to_slave[4].DATAIN
cpu_0_instruction_master_address[5] => cpu_0_instruction_master_address_to_slave[5].DATAIN
cpu_0_instruction_master_address[6] => cpu_0_instruction_master_address_to_slave[6].DATAIN
cpu_0_instruction_master_address[7] => cpu_0_instruction_master_address_to_slave[7].DATAIN
cpu_0_instruction_master_address[8] => cpu_0_instruction_master_address_to_slave[8].DATAIN
cpu_0_instruction_master_address[9] => cpu_0_instruction_master_address_to_slave[9].DATAIN
cpu_0_instruction_master_address[10] => cpu_0_instruction_master_address_to_slave[10].DATAIN
cpu_0_instruction_master_address[11] => cpu_0_instruction_master_address_to_slave[11].DATAIN
cpu_0_instruction_master_address[12] => cpu_0_instruction_master_address_to_slave[12].DATAIN
cpu_0_instruction_master_address[13] => cpu_0_instruction_master_address_to_slave[13].DATAIN
cpu_0_instruction_master_granted_cpu_0_jtag_debug_module => cpu_0_instruction_master_is_granted_some_slave~0.IN0
cpu_0_instruction_master_granted_cpu_0_jtag_debug_module => r_0~1.IN0
cpu_0_instruction_master_granted_onchip_RAM_s1 => cpu_0_instruction_master_is_granted_some_slave~0.IN1
cpu_0_instruction_master_granted_onchip_RAM_s1 => r_0~9.IN0
cpu_0_instruction_master_granted_onchip_ROM_s1 => cpu_0_instruction_master_is_granted_some_slave.IN1
cpu_0_instruction_master_granted_onchip_ROM_s1 => r_0~16.IN0
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdata~0.IN1
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => r_0~0.IN1
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => r_0~1.IN1
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => r_0~3.IN1
cpu_0_instruction_master_qualified_request_onchip_RAM_s1 => r_0~7.IN1
cpu_0_instruction_master_qualified_request_onchip_RAM_s1 => r_0~9.IN1
cpu_0_instruction_master_qualified_request_onchip_RAM_s1 => r_0~11.IN1
cpu_0_instruction_master_qualified_request_onchip_ROM_s1 => r_0~14.IN1
cpu_0_instruction_master_qualified_request_onchip_ROM_s1 => r_0~16.IN1
cpu_0_instruction_master_qualified_request_onchip_ROM_s1 => r_0~18.IN1
cpu_0_instruction_master_read => p1_cpu_0_instruction_master_latency_counter~0.IN0
cpu_0_instruction_master_read => cpu_0_instruction_master_readdata~0.IN0
cpu_0_instruction_master_read => r_0~19.IN0
cpu_0_instruction_master_read => r_0~12.IN0
cpu_0_instruction_master_read => r_0~4.IN0
cpu_0_instruction_master_read => r_0~3.IN0
cpu_0_instruction_master_read => r_0~11.IN0
cpu_0_instruction_master_read => r_0~18.IN0
cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module => cpu_0_instruction_master_readdatavalid~1.IN1
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => pre_flush_cpu_0_instruction_master_readdatavalid.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~64.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~63.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~62.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~61.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~60.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~59.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~58.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~57.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~56.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~55.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~54.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~53.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~52.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~51.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~50.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~49.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~48.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~47.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~46.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~45.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~44.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~43.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~42.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~41.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~40.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~39.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~38.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~37.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~36.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~35.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~34.IN0
cpu_0_instruction_master_read_data_valid_onchip_RAM_s1 => cpu_0_instruction_master_readdata~33.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => pre_flush_cpu_0_instruction_master_readdatavalid.IN1
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~128.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~127.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~126.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~125.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~124.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~123.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~122.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~121.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~120.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~119.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~118.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~117.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~116.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~115.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~114.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~113.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~112.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~111.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~110.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~109.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~108.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~107.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~106.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~105.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~104.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~103.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~102.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~101.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~100.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~99.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~98.IN0
cpu_0_instruction_master_read_data_valid_onchip_ROM_s1 => cpu_0_instruction_master_readdata~97.IN0
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module => r_0~0.IN0
cpu_0_instruction_master_requests_onchip_RAM_s1 => latency_load_value.IN0
cpu_0_instruction_master_requests_onchip_RAM_s1 => r_0~7.IN0
cpu_0_instruction_master_requests_onchip_ROM_s1 => latency_load_value.IN1
cpu_0_instruction_master_requests_onchip_ROM_s1 => r_0~14.IN0
cpu_0_jtag_debug_module_readdata_from_sa[0] => cpu_0_instruction_master_readdata~1.IN1
cpu_0_jtag_debug_module_readdata_from_sa[1] => cpu_0_instruction_master_readdata~2.IN1
cpu_0_jtag_debug_module_readdata_from_sa[2] => cpu_0_instruction_master_readdata~3.IN1
cpu_0_jtag_debug_module_readdata_from_sa[3] => cpu_0_instruction_master_readdata~4.IN1
cpu_0_jtag_debug_module_readdata_from_sa[4] => cpu_0_instruction_master_readdata~5.IN1
cpu_0_jtag_debug_module_readdata_from_sa[5] => cpu_0_instruction_master_readdata~6.IN1
cpu_0_jtag_debug_module_readdata_from_sa[6] => cpu_0_instruction_master_readdata~7.IN1
cpu_0_jtag_debug_module_readdata_from_sa[7] => cpu_0_instruction_master_readdata~8.IN1
cpu_0_jtag_debug_module_readdata_from_sa[8] => cpu_0_instruction_mas