led_test.hier_info

买的开发板上自带的例程

cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~172.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~171.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~170.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~169.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~168.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~167.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~166.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~165.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~164.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~163.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~162.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~161.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~160.IN0
cpu_0_data_master_write => r_1~3.IN0
cpu_0_data_master_write => r_0~39.IN1
cpu_0_data_master_write => r_0~15.IN0
cpu_0_data_master_write => r_0~5.IN0
cpu_0_data_master_write => r_0~4.IN1
cpu_0_data_master_write => r_0~14.IN0
cpu_0_data_master_write => r_1~2.IN0
cpu_0_jtag_debug_module_readdata_from_sa[0] => cpu_0_data_master_readdata~0.IN1
cpu_0_jtag_debug_module_readdata_from_sa[1] => cpu_0_data_master_readdata~1.IN1
cpu_0_jtag_debug_module_readdata_from_sa[2] => cpu_0_data_master_readdata~2.IN1
cpu_0_jtag_debug_module_readdata_from_sa[3] => cpu_0_data_master_readdata~3.IN1
cpu_0_jtag_debug_module_readdata_from_sa[4] => cpu_0_data_master_readdata~4.IN1
cpu_0_jtag_debug_module_readdata_from_sa[5] => cpu_0_data_master_readdata~5.IN1
cpu_0_jtag_debug_module_readdata_from_sa[6] => cpu_0_data_master_readdata~6.IN1
cpu_0_jtag_debug_module_readdata_from_sa[7] => cpu_0_data_master_readdata~7.IN1
cpu_0_jtag_debug_module_readdata_from_sa[8] => cpu_0_data_master_readdata~8.IN1
cpu_0_jtag_debug_module_readdata_from_sa[9] => cpu_0_data_master_readdata~9.IN1
cpu_0_jtag_debug_module_readdata_from_sa[10] => cpu_0_data_master_readdata~10.IN1
cpu_0_jtag_debug_module_readdata_from_sa[11] => cpu_0_data_master_readdata~11.IN1
cpu_0_jtag_debug_module_readdata_from_sa[12] => cpu_0_data_master_readdata~12.IN1
cpu_0_jtag_debug_module_readdata_from_sa[13] => cpu_0_data_master_readdata~13.IN1
cpu_0_jtag_debug_module_readdata_from_sa[14] => cpu_0_data_master_readdata~14.IN1
cpu_0_jtag_debug_module_readdata_from_sa[15] => cpu_0_data_master_readdata~15.IN1
cpu_0_jtag_debug_module_readdata_from_sa[16] => cpu_0_data_master_readdata~16.IN1
cpu_0_jtag_debug_module_readdata_from_sa[17] => cpu_0_data_master_readdata~17.IN1
cpu_0_jtag_debug_module_readdata_from_sa[18] => cpu_0_data_master_readdata~18.IN1
cpu_0_jtag_debug_module_readdata_from_sa[19] => cpu_0_data_master_readdata~19.IN1
cpu_0_jtag_debug_module_readdata_from_sa[20] => cpu_0_data_master_readdata~20.IN1
cpu_0_jtag_debug_module_readdata_from_sa[21] => cpu_0_data_master_readdata~21.IN1
cpu_0_jtag_debug_module_readdata_from_sa[22] => cpu_0_data_master_readdata~22.IN1
cpu_0_jtag_debug_module_readdata_from_sa[23] => cpu_0_data_master_readdata~23.IN1
cpu_0_jtag_debug_module_readdata_from_sa[24] => cpu_0_data_master_readdata~24.IN1
cpu_0_jtag_debug_module_readdata_from_sa[25] => cpu_0_data_master_readdata~25.IN1
cpu_0_jtag_debug_module_readdata_from_sa[26] => cpu_0_data_master_readdata~26.IN1
cpu_0_jtag_debug_module_readdata_from_sa[27] => cpu_0_data_master_readdata~27.IN1
cpu_0_jtag_debug_module_readdata_from_sa[28] => cpu_0_data_master_readdata~28.IN1
cpu_0_jtag_debug_module_readdata_from_sa[29] => cpu_0_data_master_readdata~29.IN1
cpu_0_jtag_debug_module_readdata_from_sa[30] => cpu_0_data_master_readdata~30.IN1
cpu_0_jtag_debug_module_readdata_from_sa[31] => cpu_0_data_master_readdata~31.IN1
d1_LED_PIO_s1_end_xfer => ~NO_FANOUT~
d1_cpu_0_jtag_debug_module_end_xfer => ~NO_FANOUT~
d1_onchip_RAM_s1_end_xfer => ~NO_FANOUT~
d1_onchip_ROM_s1_end_xfer => ~NO_FANOUT~
d1_sysid_control_slave_end_xfer => ~NO_FANOUT~
onchip_RAM_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~32.IN1
onchip_RAM_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~33.IN1
onchip_RAM_s1_readdata_from_sa[2] => cpu_0_data_master_readdata~34.IN1
onchip_RAM_s1_readdata_from_sa[3] => cpu_0_data_master_readdata~35.IN1
onchip_RAM_s1_readdata_from_sa[4] => cpu_0_data_master_readdata~36.IN1
onchip_RAM_s1_readdata_from_sa[5] => cpu_0_data_master_readdata~37.IN1
onchip_RAM_s1_readdata_from_sa[6] => cpu_0_data_master_readdata~38.IN1
onchip_RAM_s1_readdata_from_sa[7] => cpu_0_data_master_readdata~39.IN1
onchip_RAM_s1_readdata_from_sa[8] => cpu_0_data_master_readdata~40.IN1
onchip_RAM_s1_readdata_from_sa[9] => cpu_0_data_master_readdata~41.IN1
onchip_RAM_s1_readdata_from_sa[10] => cpu_0_data_master_readdata~42.IN1
onchip_RAM_s1_readdata_from_sa[11] => cpu_0_data_master_readdata~43.IN1
onchip_RAM_s1_readdata_from_sa[12] => cpu_0_data_master_readdata~44.IN1
onchip_RAM_s1_readdata_from_sa[13] => cpu_0_data_master_readdata~45.IN1
onchip_RAM_s1_readdata_from_sa[14] => cpu_0_data_master_readdata~46.IN1
onchip_RAM_s1_readdata_from_sa[15] => cpu_0_data_master_readdata~47.IN1
onchip_RAM_s1_readdata_from_sa[16] => cpu_0_data_master_readdata~48.IN1
onchip_RAM_s1_readdata_from_sa[17] => cpu_0_data_master_readdata~49.IN1
onchip_RAM_s1_readdata_from_sa[18] => cpu_0_data_master_readdata~50.IN1
onchip_RAM_s1_readdata_from_sa[19] => cpu_0_data_master_readdata~51.IN1
onchip_RAM_s1_readdata_from_sa[20] => cpu_0_data_master_readdata~52.IN1
onchip_RAM_s1_readdata_from_sa[21] => cpu_0_data_master_readdata~53.IN1
onchip_RAM_s1_readdata_from_sa[22] => cpu_0_data_master_readdata~54.IN1
onchip_RAM_s1_readdata_from_sa[23] => cpu_0_data_master_readdata~55.IN1
onchip_RAM_s1_readdata_from_sa[24] => cpu_0_data_master_readdata~56.IN1
onchip_RAM_s1_readdata_from_sa[25] => cpu_0_data_master_readdata~57.IN1
onchip_RAM_s1_readdata_from_sa[26] => cpu_0_data_master_readdata~58.IN1
onchip_RAM_s1_readdata_from_sa[27] => cpu_0_data_master_readdata~59.IN1
onchip_RAM_s1_readdata_from_sa[28] => cpu_0_data_master_readdata~60.IN1
onchip_RAM_s1_readdata_from_sa[29] => cpu_0_data_master_readdata~61.IN1
onchip_RAM_s1_readdata_from_sa[30] => cpu_0_data_master_readdata~62.IN1
onchip_RAM_s1_readdata_from_sa[31] => cpu_0_data_master_readdata~63.IN1
onchip_ROM_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~96.IN1
onchip_ROM_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~97.IN1
onchip_ROM_s1_readdata_from_sa[2] => cpu_0_data_master_readdata~98.IN1
onchip_ROM_s1_readdata_from_sa[3] => cpu_0_data_master_readdata~99.IN1
onchip_ROM_s1_readdata_from_sa[4] => cpu_0_data_master_readdata~100.IN1
onchip_ROM_s1_readdata_from_sa[5] => cpu_0_data_master_readdata~101.IN1
onchip_ROM_s1_readdata_from_sa[6] => cpu_0_data_master_readdata~102.IN1
onchip_ROM_s1_readdata_from_sa[7] => cpu_0_data_master_readdata~103.IN1
onchip_ROM_s1_readdata_from_sa[8] => cpu_0_data_master_readdata~104.IN1
onchip_ROM_s1_readdata_from_sa[9] => cpu_0_data_master_readdata~105.IN1
onchip_ROM_s1_readdata_from_sa[10] => cpu_0_data_master_readdata~106.IN1
onchip_ROM_s1_readdata_from_sa[11] => cpu_0_data_master_readdata~107.IN1
onchip_ROM_s1_readdata_from_sa[12] => cpu_0_data_master_readdata~108.IN1
onchip_ROM_s1_readdata_from_sa[13] => cpu_0_data_master_readdata~109.IN1
onchip_ROM_s1_readdata_from_sa[14] => cpu_0_data_master_readdata~110.IN1
onchip_ROM_s1_readdata_from_sa[15] => cpu_0_data_master_readdata~111.IN1
onchip_ROM_s1_readdata_from_sa[16] => cpu_0_data_master_readdata~112.IN1
onchip_ROM_s1_readdata_from_sa[17] => cpu_0_data_master_readdata~113.IN1
onchip_ROM_s1_readdata_from_sa[18] => cpu_0_data_master_readdata~114.IN1
onchip_ROM_s1_readdata_from_sa[19] => cpu_0_data_master_readdata~115.IN1
onchip_ROM_s1_readdata_from_sa[20] => cpu_0_data_master_readdata~116.IN1
onchip_ROM_s1_readdata_from_sa[21] => cpu_0_data_master_readdata~117.IN1
onchip_ROM_s1_readdata_from_sa[22] => cpu_0_data_master_readdata~118.IN1
onchip_ROM_s1_readdata_from_sa[23] => cpu_0_data_master_readdata~119.IN1
onchip_ROM_s1_readdata_from_sa[24] => cpu_0_data_master_readdata~120.IN1
onchip_ROM_s1_readdata_from_sa[25] => cpu_0_data_master_readdata~121.IN1
onchip_ROM_s1_readdata_from_sa[26] => cpu_0_data_master_readdata~122.IN1
onchip_ROM_s1_readdata_from_sa[27] => cpu_0_data_master_readdata~123.IN1
onchip_ROM_s1_readdata_from_sa[28] => cpu_0_data_master_readdata~124.IN1
onchip_ROM_s1_readdata_from_sa[29] => cpu_0_data_master_readdata~125.IN1
onchip_ROM_s1_readdata_from_sa[30] => cpu_0_data_master_readdata~126.IN1
onchip_ROM_s1_readdata_from_sa[31] => cpu_0_data_master_readdata~127.IN1
registered_cpu_0_data_master_read_data_valid_onchip_RAM_s1 => r_0~23.IN1
registered_cpu_0_data_master_read_data_valid_onchip_RAM_s1 => r_0~17.IN1
registered_cpu_0_data_master_read_data_valid_onchip_ROM_s1 => r_0~35.IN1
registered_cpu_0_data_master_read_data_valid_onchip_ROM_s1 => r_0~29.IN1
reset_n => cpu_0_data_master_waitrequest~reg0.PRESET
sysid_control_slave_readdata_from_sa[0] => cpu_0_data_master_readdata~160.IN1
sysid_control_slave_readdata_from_sa[1] => cpu_0_data_master_readdata~161.IN1
sysid_control_slave_readdata_from_sa[2] => cpu_0_data_master_readdata~162.IN1
sysid_control_slave_readdata_from_sa[3] => cpu_0_data_master_readdata~163.IN1
sysid_control_slave_readdata_from_sa[4] => cpu_0_data_master_readdata~164.IN1
sysid_control_slave_readdata_from_sa[5] => cpu_0_data_master_readdata~165.IN1
sysid_control_slave_readdata_from_sa[6] => cpu_0_data_master_readdata~166.IN1
sysid_control_slave_readdata_from_sa[7] => cpu_0_data_master_readdata~167.IN1
sysid_control_slave_readdata_from_sa[8] => cpu_0_data_master_readdata~168.IN1
sysid_control_slave_readdata_from_sa[9] => cpu_0_data_master_readdata~169.IN1
sysid_control_slave_readdata_from_sa[10] => cpu_0_data_master_readdata~170.IN1
sysid_control_slave_readdata_from_sa[11] => cpu_0_data_master_readdata~171.IN1
sysid_control_slave_readdata_from_sa[12] => cpu_0_data_master_readdata~172.IN1
sysid_control_slave_readdata_from_sa[13] => cpu_0_data_master_readdata~173.IN1
sysid_control_slave_readdata_from_sa[14] => cpu_0_data_master_readdata~174.IN1
sysid_control_slave_readdata_from_sa[15] => cpu_0_data_master_readdata~175.IN1
sysid_control_slave_readdata_from_sa[16] => cpu_0_data_master_readdata~176.IN1
sysid_control_slave_readdata_from_sa[17] => cpu_0_data_master_readdata~177.IN1
sysid_control_slave_readdata_from_sa[18] => cpu_0_data_master_readdata~178.IN1
sysid_control_slave_readdata_from_sa[19] => cpu_0_data_master_readdata~179.IN1
sysid_control_slave_readdata_from_sa[20] => cpu_0_data_master_readdata~180.IN1
sysid_control_slave_readdata_from_sa[21] => cpu_0_data_master_readdata~181.IN1
sysid_control_slave_readdata_from_sa[22] => cpu_0_data_master_readdata~182.IN1
sysid_control_slave_readdata_from_sa[23] => cpu_0_data_master_readdata~183.IN1
sysid_control_slave_readdata_from_sa[24] => cpu_0_data_master_readdata~184.IN1
sysid_control_slave_readdata_from_sa[25] => cpu_0_data_master_readdata~185.IN1
sysid_control_slave_readdata_from_sa[26] => cpu_0_data_master_readdata~186.IN1
sysid_control_slave_readdata_from_sa[27] => cpu_0_data_master_readdata~187.IN1
sysid_control_slave_readdata_from_sa[28] => cpu_0_data_master_readdata~188.IN1
sysid_control_slave_readdata_from_sa[29] => cpu_0_data_master_readdata~189.IN1
sysid_control_slave_readdata_from_sa[30] => cpu_0_data_master_readdata~190.IN1
sysid_control_slave_readdata_from_sa[31] => cpu_0_data_master_readdata~191.IN1
cpu_0_data_master_address_to_slave[0] <= cpu_0_data_master_address[0].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[1] <= cpu_0_data_master_address[1].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[2] <= cpu_0_data_master_address[2].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[3] <= cpu_0_data_master_address[3].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[4] <= cpu_0_data_master_address[4].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[5] <= cpu_0_data_master_address[5].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[6] <= cpu_0_data_master_address[6].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[7] <= cpu_0_data_master_address[7].DB_MAX_OUTPUT_PORT_TYPE