led_test.hier_info

买的开发板上自带的例程

cpu_0_data_master_address[6] => cpu_0_data_master_address_to_slave[6].DATAIN
cpu_0_data_master_address[7] => cpu_0_data_master_address_to_slave[7].DATAIN
cpu_0_data_master_address[8] => cpu_0_data_master_address_to_slave[8].DATAIN
cpu_0_data_master_address[9] => cpu_0_data_master_address_to_slave[9].DATAIN
cpu_0_data_master_address[10] => cpu_0_data_master_address_to_slave[10].DATAIN
cpu_0_data_master_address[11] => cpu_0_data_master_address_to_slave[11].DATAIN
cpu_0_data_master_address[12] => cpu_0_data_master_address_to_slave[12].DATAIN
cpu_0_data_master_address[13] => cpu_0_data_master_address_to_slave[13].DATAIN
cpu_0_data_master_debugaccess => ~NO_FANOUT~
cpu_0_data_master_granted_LED_PIO_s1 => ~NO_FANOUT~
cpu_0_data_master_granted_cpu_0_jtag_debug_module => r_0~9.IN1
cpu_0_data_master_granted_onchip_RAM_s1 => r_0~20.IN1
cpu_0_data_master_granted_onchip_ROM_s1 => r_0~32.IN1
cpu_0_data_master_granted_sysid_control_slave => ~NO_FANOUT~
cpu_0_data_master_qualified_request_LED_PIO_s1 => r_0~0.IN1
cpu_0_data_master_qualified_request_LED_PIO_s1 => r_0~1.IN0
cpu_0_data_master_qualified_request_LED_PIO_s1 => r_0~4.IN0
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_0~7.IN1
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_0~9.IN0
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_0~11.IN1
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => r_0~14.IN1
cpu_0_data_master_qualified_request_onchip_RAM_s1 => r_0~17.IN0
cpu_0_data_master_qualified_request_onchip_RAM_s1 => r_0~20.IN0
cpu_0_data_master_qualified_request_onchip_RAM_s1 => r_0~22.IN1
cpu_0_data_master_qualified_request_onchip_RAM_s1 => r_0~26.IN0
cpu_0_data_master_qualified_request_onchip_ROM_s1 => r_0~29.IN0
cpu_0_data_master_qualified_request_onchip_ROM_s1 => r_0~32.IN0
cpu_0_data_master_qualified_request_onchip_ROM_s1 => r_0~34.IN1
cpu_0_data_master_qualified_request_onchip_ROM_s1 => r_0~38.IN1
cpu_0_data_master_qualified_request_sysid_control_slave => r_1~0.IN1
cpu_0_data_master_qualified_request_sysid_control_slave => r_1~2.IN1
cpu_0_data_master_read => r_1~1.IN0
cpu_0_data_master_read => r_0~39.IN0
cpu_0_data_master_read => r_0~35.IN0
cpu_0_data_master_read => r_0~23.IN0
cpu_0_data_master_read => r_0~12.IN0
cpu_0_data_master_read => r_0~2.IN0
cpu_0_data_master_read => r_0~1.IN1
cpu_0_data_master_read => r_0~11.IN0
cpu_0_data_master_read => r_0~22.IN0
cpu_0_data_master_read => r_0~34.IN0
cpu_0_data_master_read => r_1~0.IN0
cpu_0_data_master_read_data_valid_LED_PIO_s1 => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_onchip_RAM_s1 => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_onchip_ROM_s1 => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_sysid_control_slave => ~NO_FANOUT~
cpu_0_data_master_requests_LED_PIO_s1 => r_0~0.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => r_0~7.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~31.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~30.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~29.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~28.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~27.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~26.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~25.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~24.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~23.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~22.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~21.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~20.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~19.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~18.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~17.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~16.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~15.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~14.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~13.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~12.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~11.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~10.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~9.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~8.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~7.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~6.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~5.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~4.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~3.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~2.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~1.IN0
cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_readdata~0.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => r_0~18.IN1
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~63.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~62.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~61.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~60.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~59.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~58.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~57.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~56.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~55.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~54.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~53.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~52.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~51.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~50.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~49.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~48.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~47.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~46.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~45.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~44.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~43.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~42.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~41.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~40.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~39.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~38.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~37.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~36.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~35.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~34.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~33.IN0
cpu_0_data_master_requests_onchip_RAM_s1 => cpu_0_data_master_readdata~32.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => r_0~30.IN1
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~127.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~126.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~125.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~124.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~123.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~122.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~121.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~120.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~119.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~118.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~117.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~116.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~115.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~114.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~113.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~112.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~111.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~110.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~109.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~108.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~107.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~106.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~105.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~104.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~103.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~102.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~101.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~100.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~99.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~98.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~97.IN0
cpu_0_data_master_requests_onchip_ROM_s1 => cpu_0_data_master_readdata~96.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~191.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~190.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~189.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~188.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~187.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~186.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~185.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~184.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~183.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~182.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~181.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~180.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~179.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~178.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~177.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~176.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~175.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~174.IN0
cpu_0_data_master_requests_sysid_control_slave => cpu_0_data_master_readdata~173.IN0