led_test.hier_info

买的开发板上自带的例程

|led_test
LED_PIO <= first_nios2_system:inst.out_port_from_the_LED_PIO
clk => first_nios2_system:inst.clk
reset_n => first_nios2_system:inst.reset_n


|led_test|first_nios2_system:inst
clk => clk~0.IN13
reset_n => reset_n_sources~0.IN1
out_port_from_the_LED_PIO <= LED_PIO:the_LED_PIO.out_port


|led_test|first_nios2_system:inst|LED_PIO_s1_arbitrator:the_LED_PIO_s1
clk => d1_reasons_to_wait.CLK
clk => d1_LED_PIO_s1_end_xfer~reg0.CLK
cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[2] => LED_PIO_s1_address[0].DATAIN
cpu_0_data_master_address_to_slave[3] => LED_PIO_s1_address[1].DATAIN
cpu_0_data_master_address_to_slave[4] => Equal0.IN9
cpu_0_data_master_address_to_slave[5] => Equal0.IN8
cpu_0_data_master_address_to_slave[6] => Equal0.IN7
cpu_0_data_master_address_to_slave[7] => Equal0.IN6
cpu_0_data_master_address_to_slave[8] => Equal0.IN5
cpu_0_data_master_address_to_slave[9] => Equal0.IN4
cpu_0_data_master_address_to_slave[10] => Equal0.IN3
cpu_0_data_master_address_to_slave[11] => Equal0.IN0
cpu_0_data_master_address_to_slave[12] => Equal0.IN2
cpu_0_data_master_address_to_slave[13] => Equal0.IN1
cpu_0_data_master_read => LED_PIO_s1_in_a_read_cycle.IN0
cpu_0_data_master_read => cpu_0_data_master_requests_LED_PIO_s1~0.IN1
cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_LED_PIO_s1~0.IN0
cpu_0_data_master_write => LED_PIO_s1_write_n~0.IN0
cpu_0_data_master_write => cpu_0_data_master_qualified_request_LED_PIO_s1~0.IN1
cpu_0_data_master_write => cpu_0_data_master_requests_LED_PIO_s1~2.IN0
cpu_0_data_master_write => cpu_0_data_master_requests_LED_PIO_s1~0.IN0
cpu_0_data_master_writedata[0] => LED_PIO_s1_writedata.DATAIN
cpu_0_data_master_writedata[1] => ~NO_FANOUT~
cpu_0_data_master_writedata[2] => ~NO_FANOUT~
cpu_0_data_master_writedata[3] => ~NO_FANOUT~
cpu_0_data_master_writedata[4] => ~NO_FANOUT~
cpu_0_data_master_writedata[5] => ~NO_FANOUT~
cpu_0_data_master_writedata[6] => ~NO_FANOUT~
cpu_0_data_master_writedata[7] => ~NO_FANOUT~
cpu_0_data_master_writedata[8] => ~NO_FANOUT~
cpu_0_data_master_writedata[9] => ~NO_FANOUT~
cpu_0_data_master_writedata[10] => ~NO_FANOUT~
cpu_0_data_master_writedata[11] => ~NO_FANOUT~
cpu_0_data_master_writedata[12] => ~NO_FANOUT~
cpu_0_data_master_writedata[13] => ~NO_FANOUT~
cpu_0_data_master_writedata[14] => ~NO_FANOUT~
cpu_0_data_master_writedata[15] => ~NO_FANOUT~
cpu_0_data_master_writedata[16] => ~NO_FANOUT~
cpu_0_data_master_writedata[17] => ~NO_FANOUT~
cpu_0_data_master_writedata[18] => ~NO_FANOUT~
cpu_0_data_master_writedata[19] => ~NO_FANOUT~
cpu_0_data_master_writedata[20] => ~NO_FANOUT~
cpu_0_data_master_writedata[21] => ~NO_FANOUT~
cpu_0_data_master_writedata[22] => ~NO_FANOUT~
cpu_0_data_master_writedata[23] => ~NO_FANOUT~
cpu_0_data_master_writedata[24] => ~NO_FANOUT~
cpu_0_data_master_writedata[25] => ~NO_FANOUT~
cpu_0_data_master_writedata[26] => ~NO_FANOUT~
cpu_0_data_master_writedata[27] => ~NO_FANOUT~
cpu_0_data_master_writedata[28] => ~NO_FANOUT~
cpu_0_data_master_writedata[29] => ~NO_FANOUT~
cpu_0_data_master_writedata[30] => ~NO_FANOUT~
cpu_0_data_master_writedata[31] => ~NO_FANOUT~
reset_n => LED_PIO_s1_reset_n.DATAIN
reset_n => d1_reasons_to_wait.ACLR
reset_n => d1_LED_PIO_s1_end_xfer~reg0.PRESET
LED_PIO_s1_address[0] <= cpu_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE
LED_PIO_s1_address[1] <= cpu_0_data_master_address_to_slave[3].DB_MAX_OUTPUT_PORT_TYPE
LED_PIO_s1_chipselect <= cpu_0_data_master_qualified_request_LED_PIO_s1~1.DB_MAX_OUTPUT_PORT_TYPE
LED_PIO_s1_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE
LED_PIO_s1_write_n <= LED_PIO_s1_write_n~0.DB_MAX_OUTPUT_PORT_TYPE
LED_PIO_s1_writedata <= cpu_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_granted_LED_PIO_s1 <= cpu_0_data_master_qualified_request_LED_PIO_s1~1.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_qualified_request_LED_PIO_s1 <= cpu_0_data_master_qualified_request_LED_PIO_s1~1.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_read_data_valid_LED_PIO_s1 <= <GND>
cpu_0_data_master_requests_LED_PIO_s1 <= cpu_0_data_master_requests_LED_PIO_s1~2.DB_MAX_OUTPUT_PORT_TYPE
d1_LED_PIO_s1_end_xfer <= d1_LED_PIO_s1_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE


|led_test|first_nios2_system:inst|LED_PIO:the_LED_PIO
address[0] => Equal0.IN30
address[1] => Equal0.IN31
chipselect => always0~0.IN1
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0~0.IN0
writedata => data_out.DATAIN
out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE


|led_test|first_nios2_system:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module
clk => d1_reasons_to_wait.CLK
clk => cpu_0_jtag_debug_module_arb_share_counter.CLK
clk => cpu_0_jtag_debug_module_slavearbiterlockenable.CLK
clk => last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module.CLK
clk => last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module.CLK
clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[1].CLK
clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[0].CLK
clk => cpu_0_jtag_debug_module_arb_addend[1].CLK
clk => cpu_0_jtag_debug_module_arb_addend[0].CLK
clk => cpu_0_jtag_debug_module_reg_firsttransfer.CLK
clk => d1_cpu_0_jtag_debug_module_end_xfer~reg0.CLK
cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[2] => cpu_0_jtag_debug_module_address~8.DATAB
cpu_0_data_master_address_to_slave[3] => cpu_0_jtag_debug_module_address~7.DATAB
cpu_0_data_master_address_to_slave[4] => cpu_0_jtag_debug_module_address~6.DATAB
cpu_0_data_master_address_to_slave[5] => cpu_0_jtag_debug_module_address~5.DATAB
cpu_0_data_master_address_to_slave[6] => cpu_0_jtag_debug_module_address~4.DATAB
cpu_0_data_master_address_to_slave[7] => cpu_0_jtag_debug_module_address~3.DATAB
cpu_0_data_master_address_to_slave[8] => cpu_0_jtag_debug_module_address~2.DATAB
cpu_0_data_master_address_to_slave[9] => cpu_0_jtag_debug_module_address~1.DATAB
cpu_0_data_master_address_to_slave[10] => cpu_0_jtag_debug_module_address~0.DATAB
cpu_0_data_master_address_to_slave[11] => Equal0.IN1
cpu_0_data_master_address_to_slave[12] => Equal0.IN24
cpu_0_data_master_address_to_slave[13] => Equal0.IN0
cpu_0_data_master_byteenable[0] => cpu_0_jtag_debug_module_byteenable~3.DATAB
cpu_0_data_master_byteenable[1] => cpu_0_jtag_debug_module_byteenable~2.DATAB
cpu_0_data_master_byteenable[2] => cpu_0_jtag_debug_module_byteenable~1.DATAB
cpu_0_data_master_byteenable[3] => cpu_0_jtag_debug_module_byteenable~0.DATAB
cpu_0_data_master_debugaccess => cpu_0_jtag_debug_module_debugaccess.DATAIN
cpu_0_data_master_read => cpu_0_jtag_debug_module_in_a_read_cycle~0.IN0
cpu_0_data_master_read => cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN1
cpu_0_data_master_waitrequest => cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module~0.IN0
cpu_0_data_master_write => cpu_0_jtag_debug_module_write~0.IN0
cpu_0_data_master_write => cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module~0.IN1
cpu_0_data_master_write => cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN0
cpu_0_data_master_writedata[0] => cpu_0_jtag_debug_module_writedata[0].DATAIN
cpu_0_data_master_writedata[1] => cpu_0_jtag_debug_module_writedata[1].DATAIN
cpu_0_data_master_writedata[2] => cpu_0_jtag_debug_module_writedata[2].DATAIN
cpu_0_data_master_writedata[3] => cpu_0_jtag_debug_module_writedata[3].DATAIN
cpu_0_data_master_writedata[4] => cpu_0_jtag_debug_module_writedata[4].DATAIN
cpu_0_data_master_writedata[5] => cpu_0_jtag_debug_module_writedata[5].DATAIN
cpu_0_data_master_writedata[6] => cpu_0_jtag_debug_module_writedata[6].DATAIN
cpu_0_data_master_writedata[7] => cpu_0_jtag_debug_module_writedata[7].DATAIN
cpu_0_data_master_writedata[8] => cpu_0_jtag_debug_module_writedata[8].DATAIN
cpu_0_data_master_writedata[9] => cpu_0_jtag_debug_module_writedata[9].DATAIN
cpu_0_data_master_writedata[10] => cpu_0_jtag_debug_module_writedata[10].DATAIN
cpu_0_data_master_writedata[11] => cpu_0_jtag_debug_module_writedata[11].DATAIN
cpu_0_data_master_writedata[12] => cpu_0_jtag_debug_module_writedata[12].DATAIN
cpu_0_data_master_writedata[13] => cpu_0_jtag_debug_module_writedata[13].DATAIN
cpu_0_data_master_writedata[14] => cpu_0_jtag_debug_module_writedata[14].DATAIN
cpu_0_data_master_writedata[15] => cpu_0_jtag_debug_module_writedata[15].DATAIN
cpu_0_data_master_writedata[16] => cpu_0_jtag_debug_module_writedata[16].DATAIN
cpu_0_data_master_writedata[17] => cpu_0_jtag_debug_module_writedata[17].DATAIN
cpu_0_data_master_writedata[18] => cpu_0_jtag_debug_module_writedata[18].DATAIN
cpu_0_data_master_writedata[19] => cpu_0_jtag_debug_module_writedata[19].DATAIN
cpu_0_data_master_writedata[20] => cpu_0_jtag_debug_module_writedata[20].DATAIN
cpu_0_data_master_writedata[21] => cpu_0_jtag_debug_module_writedata[21].DATAIN
cpu_0_data_master_writedata[22] => cpu_0_jtag_debug_module_writedata[22].DATAIN
cpu_0_data_master_writedata[23] => cpu_0_jtag_debug_module_writedata[23].DATAIN
cpu_0_data_master_writedata[24] => cpu_0_jtag_debug_module_writedata[24].DATAIN
cpu_0_data_master_writedata[25] => cpu_0_jtag_debug_module_writedata[25].DATAIN
cpu_0_data_master_writedata[26] => cpu_0_jtag_debug_module_writedata[26].DATAIN
cpu_0_data_master_writedata[27] => cpu_0_jtag_debug_module_writedata[27].DATAIN
cpu_0_data_master_writedata[28] => cpu_0_jtag_debug_module_writedata[28].DATAIN
cpu_0_data_master_writedata[29] => cpu_0_jtag_debug_module_writedata[29].DATAIN
cpu_0_data_master_writedata[30] => cpu_0_jtag_debug_module_writedata[30].DATAIN
cpu_0_data_master_writedata[31] => cpu_0_jtag_debug_module_writedata[31].DATAIN
cpu_0_instruction_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_instruction_master_address_to_slave[1] => ~NO_FANOUT~