prev_cmp_led_test.qmsg

买的开发板上自带的例程

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_oeb1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_oeb1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_oeb1 " "Info: Found entity 1: altsyncram_oeb1" {  } { { "db/altsyncram_oeb1.tdf" "" { Text "F:/alter/2sfenpin/liz/led_test/db/altsyncram_oeb1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_oeb1 first_nios2_system:inst\|onchip_RAM:the_onchip_RAM\|altsyncram:the_altsyncram\|altsyncram_oeb1:auto_generated " "Info: Elaborating entity \"altsyncram_oeb1\" for hierarchy \"first_nios2_system:inst\|onchip_RAM:the_onchip_RAM\|altsyncram:the_altsyncram\|altsyncram_oeb1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_ROM_s1_arbitrator first_nios2_system:inst\|onchip_ROM_s1_arbitrator:the_onchip_ROM_s1 " "Info: Elaborating entity \"onchip_ROM_s1_arbitrator\" for hierarchy \"first_nios2_system:inst\|onchip_ROM_s1_arbitrator:the_onchip_ROM_s1\"" {  } { { "first_nios2_system.v" "the_onchip_ROM_s1" { Text "F:/alter/2sfenpin/liz/led_test/first_nios2_system.v" 2651 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "onchip_ROM.v 1 1 " "Warning: Using design file onchip_ROM.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 onchip_ROM " "Info: Found entity 1: onchip_ROM" {  } { { "onchip_ROM.v" "" { Text "F:/alter/2sfenpin/liz/led_test/onchip_ROM.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "onchip_ROM first_nios2_system:inst\|onchip_ROM:the_onchip_ROM " "Info: Elaborating entity \"onchip_ROM\" for hierarchy \"first_nios2_system:inst\|onchip_ROM:the_onchip_ROM\"" {  } { { "first_nios2_system.v" "the_onchip_ROM" { Text "F:/alter/2sfenpin/liz/led_test/first_nios2_system.v" 2664 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram first_nios2_system:inst\|onchip_ROM:the_onchip_ROM\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"first_nios2_system:inst\|onchip_ROM:the_onchip_ROM\|altsyncram:the_altsyncram\"" {  } { { "onchip_ROM.v" "the_altsyncram" { Text "F:/alter/2sfenpin/liz/led_test/onchip_ROM.v" 92 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "first_nios2_system:inst\|onchip_ROM:the_onchip_ROM\|altsyncram:the_altsyncram " "Info: Elaborated megafunction instantiation \"first_nios2_system:inst\|onchip_ROM:the_onchip_ROM\|altsyncram:the_altsyncram\"" {  } { { "onchip_ROM.v" "" { Text "F:/alter/2sfenpin/liz/led_test/onchip_ROM.v" 92 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_teb1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_teb1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_teb1 " "Info: Found entity 1: altsyncram_teb1" {  } { { "db/altsyncram_teb1.tdf" "" { Text "F:/alter/2sfenpin/liz/led_test/db/altsyncram_teb1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_teb1 first_nios2_system:inst\|onchip_ROM:the_onchip_ROM\|altsyncram:the_altsyncram\|altsyncram_teb1:auto_generated " "Info: Elaborating entity \"altsyncram_teb1\" for hierarchy \"first_nios2_system:inst\|onchip_ROM:the_onchip_ROM\|altsyncram:the_altsyncram\|altsyncram_teb1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sysid_control_slave_arbitrator first_nios2_system:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave " "Info: Elaborating entity \"sysid_control_slave_arbitrator\" for hierarchy \"first_nios2_system:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave\"" {  } { { "first_nios2_system.v" "the_sysid_control_slave" { Text "F:/alter/2sfenpin/liz/led_test/first_nios2_system.v" 2681 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "sysid.v 1 1 " "Warning: Using design file sysid.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sysid " "Info: Found entity 1: sysid" {  } { { "sysid.v" "" { Text "F:/alter/2sfenpin/liz/led_test/sysid.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sysid first_nios2_system:inst\|sysid:the_sysid " "Info: Elaborating entity \"sysid\" for hierarchy \"first_nios2_system:inst\|sysid:the_sysid\"" {  } { { "first_nios2_system.v" "the_sysid" { Text "F:/alter/2sfenpin/liz/led_test/first_nios2_system.v" 2687 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "first_nios2_system_reset_clk_domain_synch_module first_nios2_system:inst\|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch " "Info: Elaborating entity \"first_nios2_system_reset_clk_domain_synch_module\" for hierarchy \"first_nios2_system:inst\|first_nios2_system_reset_clk_domain_synch_module:first_nios2_system_reset_clk_domain_synch\"" {  } { { "first_nios2_system.v" "first_nios2_system_reset_clk_domain_synch" { Text "F:/alter/2sfenpin/liz/led_test/first_nios2_system.v" 2696 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "address_b cpu_0_traceram_lpm_dram_bdp_component 17 7 " "Warning (12020): Port \"address_b\" on the entity instantiation of \"cpu_0_traceram_lpm_dram_bdp_component\" is connected to a signal of width 17. The formal width of the signal in the module is 7.  Extra bits will be ignored." {  } { { "cpu_0.v" "cpu_0_traceram_lpm_dram_bdp_component" { Text "F:/alter/2sfenpin/liz/led_test/cpu_0.v" 3201 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "jdo the_cpu_0_nios2_oci_itrace 38 16 " "Warning (12020): Port \"jdo\" on the entity instantiation of \"the_cpu_0_nios2_oci_itrace\" is connected to a signal of width 38. The formal width of the signal in the module is 16.  Extra bits will be ignored." {  } { { "cpu_0.v" "the_cpu_0_nios2_oci_itrace" { Text "F:/alter/2sfenpin/liz/led_test/cpu_0.v" 3641 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrk cpu_0_nios2_oci_dbrk_hit3_match_single 78 71 " "Warning (12020): Port \"dbrk\" on the entity instantiation of \"cpu_0_nios2_oci_dbrk_hit3_match_single\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu_0.v" "cpu_0_nios2_oci_dbrk_hit3_match_single" { Text "F:/alter/2sfenpin/liz/led_test/cpu_0.v" 1837 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrk cpu_0_nios2_oci_dbrk_hit2_match_single 78 71 " "Warning (12020): Port \"dbrk\" on the entity instantiation of \"cpu_0_nios2_oci_dbrk_hit2_match_single\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu_0.v" "cpu_0_nios2_oci_dbrk_hit2_match_single" { Text "F:/alter/2sfenpin/liz/led_test/cpu_0.v" 1825 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrka cpu_0_nios2_oci_dbrk_hit2_match_paired 78 71 " "Warning (12020): Port \"dbrka\" on the entity instantiation of \"cpu_0_nios2_oci_dbrk_hit2_match_paired\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu_0.v" "cpu_0_nios2_oci_dbrk_hit2_match_paired" { Text "F:/alter/2sfenpin/liz/led_test/cpu_0.v" 1814 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrkb cpu_0_nios2_oci_dbrk_hit2_match_paired 78 71 " "Warning (12020): Port \"dbrkb\" on the entity instantiation of \"cpu_0_nios2_oci_dbrk_hit2_match_paired\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu_0.v" "cpu_0_nios2_oci_dbrk_hit2_match_paired" { Text "F:/alter/2sfenpin/liz/led_test/cpu_0.v" 1814 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "dbrk cpu_0_nios2_oci_dbrk_hit1_match_single 78 71 " "Warning (12020): Port \"dbrk\" on the entity instantiation of \"cpu_0_nios2_oci_dbrk_hit1_match_single\" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be ignored." {  } { { "cpu_0.v" "cpu_0_nios2_oci_dbrk_hit1_match_single" { Text "F:/alter/2sfenpin/liz/led_test/cpu_0.v" 1801 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits w