📄 first_nios2_system.ptf.bak
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{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "0cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "1024";
Read_Latency = "1";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "8";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
Offset_Address = "0x00002400";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
Offset_Address = "0x00002400";
}
Base_Address = "0x00002400";
Address_Group = "0";
Has_IRQ = "0";
Is_Channel = "1";
Is_Writable = "1";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
iss_model_name = "altera_memory";
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M4K";
init_contents_file = "onchip_RAM";
non_default_init_file_enabled = "0";
gui_ram_block_type = "Automatic";
Writeable = "1";
dual_port = "0";
Size_Value = "1024";
Size_Multiple = "1";
use_shallow_mem_blocks = "0";
init_mem_content = "1";
allow_in_system_memory_content_editor = "0";
instance_id = "NONE";
ignore_auto_block_type_assignment = "1";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
View
{
MESSAGES
{
}
}
}
class = "altera_avalon_onchip_memory2";
class_version = "7.07";
HDL_INFO
{
}
SLAVE s2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Group = "0";
Address_Alignment = "dynamic";
Address_Width = "8";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "1024";
Read_Latency = "1";
Is_Channel = "1";
Is_Enabled = "0";
Is_Writable = "1";
}
}
}
MODULE LED_PIO
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "1";
Address_Width = "2";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
Offset_Address = "0x00002800";
}
Base_Address = "0x00002800";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
Is_Readable = "0";
Is_Writable = "1";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "1";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "1";
}
}
class = "altera_avalon_pio";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
Date_Modified = "";
View
{
MESSAGES
{
}
Settings_Summary = " 1-bit PIO using <br>
output pins";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "1";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
}
HDL_INFO
{
# The list of files associated with this module (for synthesis
# and other purposes) depends on the users' wizard-choices.
# This section will be filled-in by the Generator_Program
# after the module logic has been created and the
# various filenames are known.
}
}
MODULE sysid
{
SLAVE control_slave
{
PORT_WIRING
{
PORT clock
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
Offset_Address = "0x00002810";
}
Base_Address = "0x00002810";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
class = "altera_avalon_sysid";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
View
{
Settings_Summary = "No system ID yet. <br>
A unique ID is assigned every time <br>
the system is generated.";
MESSAGES
{
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
id = "148173920";
timestamp = "1225933793";
regenerate_values = "0";
}
HDL_INFO
{
# The list of files associated with this module (for synthesis
# and other purposes) depends on the users' wizard-choices.
# This section will be filled-in by the Generator_Program
# after the module logic has been created and the
# various filenames are known.
}
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program
# after the module logic has been created and the ports are known.
#
}
}
}
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