beep.tan.qmsg

买的开发板上自带的例程

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "beep.bdf" "" { Schematic "F:/alter/2sfenpin/liz/beep_2c5/beep.bdf" { { 240 -64 104 256 "clk" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~UPDATEUSER " "Info: Assuming node \"altera_internal_jtag~UPDATEUSER\" is an undefined clock" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~UPDATEUSER" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register beep_cup:inst\|cpu_0:the_cpu_0\|R_logic_op\[0\] register beep_cup:inst\|cpu_0:the_cpu_0\|W_cmp_result 108.87 MHz 9.185 ns Internal " "Info: Clock \"clk\" has Internal fmax of 108.87 MHz between source register \"beep_cup:inst\|cpu_0:the_cpu_0\|R_logic_op\[0\]\" and destination register \"beep_cup:inst\|cpu_0:the_cpu_0\|W_cmp_result\" (period= 9.185 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.921 ns + Longest register register " "Info: + Longest register to register delay is 8.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns beep_cup:inst\|cpu_0:the_cpu_0\|R_logic_op\[0\] 1 REG LCFF_X10_Y7_N1 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y7_N1; Fanout = 33; REG Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|R_logic_op\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] } "NODE_NAME" } } { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 4917 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.624 ns) 1.866 ns beep_cup:inst\|cpu_0:the_cpu_0\|E_logic_result\[15\]~8564 2 COMB LCCOMB_X10_Y6_N4 2 " "Info: 2: + IC(1.242 ns) + CELL(0.624 ns) = 1.866 ns; Loc. = LCCOMB_X10_Y6_N4; Fanout = 2; COMB Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|E_logic_result\[15\]~8564'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.866 ns" { beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] beep_cup:inst|cpu_0:the_cpu_0|E_logic_result[15]~8564 } "NODE_NAME" } } { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 4104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.819 ns) + CELL(0.202 ns) 3.887 ns beep_cup:inst\|cpu_0:the_cpu_0\|Equal127~852 3 COMB LCCOMB_X12_Y7_N24 1 " "Info: 3: + IC(1.819 ns) + CELL(0.202 ns) = 3.887 ns; Loc. = LCCOMB_X12_Y7_N24; Fanout = 1; COMB Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|Equal127~852'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.021 ns" { beep_cup:inst|cpu_0:the_cpu_0|E_logic_result[15]~8564 beep_cup:inst|cpu_0:the_cpu_0|Equal127~852 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.458 ns) + CELL(0.206 ns) 5.551 ns beep_cup:inst\|cpu_0:the_cpu_0\|Equal127~853 4 COMB LCCOMB_X14_Y6_N18 1 " "Info: 4: + IC(1.458 ns) + CELL(0.206 ns) = 5.551 ns; Loc. = LCCOMB_X14_Y6_N18; Fanout = 1; COMB Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|Equal127~853'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.664 ns" { beep_cup:inst|cpu_0:the_cpu_0|Equal127~852 beep_cup:inst|cpu_0:the_cpu_0|Equal127~853 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.344 ns) + CELL(0.206 ns) 7.101 ns beep_cup:inst\|cpu_0:the_cpu_0\|Equal127~859 5 COMB LCCOMB_X13_Y10_N28 1 " "Info: 5: + IC(1.344 ns) + CELL(0.206 ns) = 7.101 ns; Loc. = LCCOMB_X13_Y10_N28; Fanout = 1; COMB Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|Equal127~859'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.550 ns" { beep_cup:inst|cpu_0:the_cpu_0|Equal127~853 beep_cup:inst|cpu_0:the_cpu_0|Equal127~859 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.506 ns) + CELL(0.206 ns) 8.813 ns beep_cup:inst\|cpu_0:the_cpu_0\|E_cmp_result~100 6 COMB LCCOMB_X10_Y7_N16 1 " "Info: 6: + IC(1.506 ns) + CELL(0.206 ns) = 8.813 ns; Loc. = LCCOMB_X10_Y7_N16; Fanout = 1; COMB Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|E_cmp_result~100'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.712 ns" { beep_cup:inst|cpu_0:the_cpu_0|Equal127~859 beep_cup:inst|cpu_0:the_cpu_0|E_cmp_result~100 } "NODE_NAME" } } { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 4099 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.921 ns beep_cup:inst\|cpu_0:the_cpu_0\|W_cmp_result 7 REG LCFF_X10_Y7_N17 2 " "Info: 7: + IC(0.000 ns) + CELL(0.108 ns) = 8.921 ns; Loc. = LCFF_X10_Y7_N17; Fanout = 2; REG Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|W_cmp_result'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { beep_cup:inst|cpu_0:the_cpu_0|E_cmp_result~100 beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result } "NODE_NAME" } } { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 4355 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.552 ns ( 17.40 % ) " "Info: Total cell delay = 1.552 ns ( 17.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.369 ns ( 82.60 % ) " "Info: Total interconnect delay = 7.369 ns ( 82.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.921 ns" { beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] beep_cup:inst|cpu_0:the_cpu_0|E_logic_result[15]~8564 beep_cup:inst|cpu_0:the_cpu_0|Equal127~852 beep_cup:inst|cpu_0:the_cpu_0|Equal127~853 beep_cup:inst|cpu_0:the_cpu_0|Equal127~859 beep_cup:inst|cpu_0:the_cpu_0|E_cmp_result~100 beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.921 ns" { beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] {} beep_cup:inst|cpu_0:the_cpu_0|E_logic_result[15]~8564 {} beep_cup:inst|cpu_0:the_cpu_0|Equal127~852 {} beep_cup:inst|cpu_0:the_cpu_0|Equal127~853 {} beep_cup:inst|cpu_0:the_cpu_0|Equal127~859 {} beep_cup:inst|cpu_0:the_cpu_0|E_cmp_result~100 {} beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result {} } { 0.000ns 1.242ns 1.819ns 1.458ns 1.344ns 1.506ns 0.000ns } { 0.000ns 0.624ns 0.202ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.760 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "beep.bdf" "" { Schematic "F:/alter/2sfenpin/liz/beep_2c5/beep.bdf" { { 240 -64 104 256 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 1111 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 1111; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "beep.bdf" "" { Schematic "F:/alter/2sfenpin/liz/beep_2c5/beep.bdf" { { 240 -64 104 256 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.666 ns) 2.760 ns beep_cup:inst\|cpu_0:the_cpu_0\|W_cmp_result 3 REG LCFF_X10_Y7_N17 2 " "Info: 3: + IC(0.811 ns) + CELL(0.666 ns) = 2.760 ns; Loc. = LCFF_X10_Y7_N17; Fanout = 2; REG Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|W_cmp_result'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { clk~clkctrl beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result } "NODE_NAME" } } { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 4355 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.43 % ) " "Info: Total cell delay = 1.806 ns ( 65.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.954 ns ( 34.57 % ) " "Info: Total interconnect delay = 0.954 ns ( 34.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.760 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "beep.bdf" "" { Schematic "F:/alter/2sfenpin/liz/beep_2c5/beep.bdf" { { 240 -64 104 256 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 1111 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 1111; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "beep.bdf" "" { Schematic "F:/alter/2sfenpin/liz/beep_2c5/beep.bdf" { { 240 -64 104 256 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.666 ns) 2.760 ns beep_cup:inst\|cpu_0:the_cpu_0\|R_logic_op\[0\] 3 REG LCFF_X10_Y7_N1 33 " "Info: 3: + IC(0.811 ns) + CELL(0.666 ns) = 2.760 ns; Loc. = LCFF_X10_Y7_N1; Fanout = 33; REG Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|R_logic_op\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { clk~clkctrl beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] } "NODE_NAME" } } { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 4917 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.43 % ) " "Info: Total cell delay = 1.806 ns ( 65.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.954 ns ( 34.57 % ) " "Info: Total interconnect delay = 0.954 ns ( 34.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 4917 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 4355 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.921 ns" { beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] beep_cup:inst|cpu_0:the_cpu_0|E_logic_result[15]~8564 beep_cup:inst|cpu_0:the_cpu_0|Equal127~852 beep_cup:inst|cpu_0:the_cpu_0|Equal127~853 beep_cup:inst|cpu_0:the_cpu_0|Equal127~859 beep_cup:inst|cpu_0:the_cpu_0|E_cmp_result~100 beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.921 ns" { beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] {} beep_cup:inst|cpu_0:the_cpu_0|E_logic_result[15]~8564 {} beep_cup:inst|cpu_0:the_cpu_0|Equal127~852 {} beep_cup:inst|cpu_0:the_cpu_0|Equal127~853 {} beep_cup:inst|cpu_0:the_cpu_0|Equal127~859 {} beep_cup:inst|cpu_0:the_cpu_0|E_cmp_result~100 {} beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result {} } { 0.000ns 1.242ns 1.819ns 1.458ns 1.344ns 1.506ns 0.000ns } { 0.000ns 0.624ns 0.202ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} beep_cup:inst|cpu_0:the_cpu_0|W_cmp_result {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} beep_cup:inst|cpu_0:the_cpu_0|R_logic_op[0] {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}