beep.hif

买的开发板上自带的例程

db|beep.(21).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(addr)
13 downto 0
PARAMETER_STRING
USR
 constraint(data)
31 downto 0
PARAMETER_STRING
USR
 constraint(dbrk)
70 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit0_match_single
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit1_match_single
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit2_match_single
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit3_match_single
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_nios2_oci_itrace
# storage
db|beep.(22).cnf
db|beep.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(jdo)
15 downto 0
PARAMETER_STRING
USR
 constraint(itm)
35 downto 0
PARAMETER_STRING
USR
 constraint(trc_ctrl)
15 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_nios2_oci_dtrace
# storage
db|beep.(23).cnf
db|beep.(23).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(cpu_d_address)
13 downto 0
PARAMETER_STRING
USR
 constraint(cpu_d_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_d_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(trc_ctrl)
15 downto 0
PARAMETER_STRING
USR
 constraint(atm)
35 downto 0
PARAMETER_STRING
USR
 constraint(dtm)
35 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_nios2_oci_td_mode
# storage
db|beep.(24).cnf
db|beep.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(ctrl)
8 downto 0
PARAMETER_STRING
USR
 constraint(td_mode)
3 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_nios2_oci_fifo
# storage
db|beep.(25).cnf
db|beep.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(atm)
35 downto 0
PARAMETER_STRING
USR
 constraint(dtm)
35 downto 0
PARAMETER_STRING
USR
 constraint(itm)
35 downto 0
PARAMETER_STRING
USR
 constraint(tw)
35 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_nios2_oci_compute_tm_count
# storage
db|beep.(26).cnf
db|beep.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(compute_tm_count)
1 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_nios2_oci_fifowp_inc
# storage
db|beep.(27).cnf
db|beep.(27).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(tm_count)
1 downto 0
PARAMETER_STRING
USR
 constraint(fifowp_inc)
3 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_nios2_oci_fifocount_inc
# storage
db|beep.(28).cnf
db|beep.(28).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(tm_count)
1 downto 0
PARAMETER_STRING
USR
 constraint(fifocount_inc)
4 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_nios2_oci_pib
# storage
db|beep.(29).cnf
db|beep.(29).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(tw)
35 downto 0
PARAMETER_STRING
USR
 constraint(tr_data)
17 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_nios2_oci_im
# storage
db|beep.(30).cnf
db|beep.(30).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(jdo)
37 downto 0
PARAMETER_STRING
USR
 constraint(trc_ctrl)
15 downto 0
PARAMETER_STRING
USR
 constraint(tw)
35 downto 0
PARAMETER_STRING
USR
 constraint(tracemem_trcdata)
35 downto 0
PARAMETER_STRING
USR
 constraint(trc_im_addr)
6 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_traceram_lpm_dram_bdp_component_module
# storage
db|beep.(31).cnf
db|beep.(31).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_file

PARAMETER_STRING
USR
 constraint(address_a)
6 downto 0
PARAMETER_STRING
USR
 constraint(address_b)
6 downto 0
PARAMETER_STRING
USR
 constraint(data_a)
35 downto 0
PARAMETER_STRING
USR
 constraint(data_b)
35 downto 0
PARAMETER_STRING
USR
 constraint(q_a)
35 downto 0
PARAMETER_STRING
USR
 constraint(q_b)
35 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
altsyncram
# storage
db|beep.(32).cnf
db|beep.(32).cnf
# case_insensitive
# source_file
d:|altera|72|quartus|libraries|megafunctions|altsyncram.tdf
56e814d9f431d4c82859865aa9372
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
36
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
128
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
36
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
7
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
128
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE

PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_e502
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a35
-1
3
q_a34
-1
3
q_a33
-1
3
q_a32
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b35
-1
3
data_b34
-1
3
data_b33
-1
3
data_b32
-1
3
data_b31
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data_b30
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3
data_b3
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3
data_b29
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3
data_b28
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3
data_b27
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3
data_b26
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3
data_b25
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3
data_b24
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3
data_b23
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data_b22
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3
data_b21
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3
data_b20
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3
data_b2
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3
data_b19
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3
data_b18
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data_b17
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3
data_b16
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3
data_b15
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data_b14
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data_b13
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3
data_b12
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data_b11
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data_b10
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data_b1
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data_b0
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data_a9
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3
data_a8
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data_a7
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data_a6
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3
data_a5
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3
data_a4
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data_a35
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data_a34
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3
data_a33
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3
data_a32