beep.hif

买的开发板上自带的例程

Version 7.2 Build 151 09/26/2007 SJ Full Version
11
920
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
beep
# storage
db|beep.(0).cnf
db|beep.(0).cnf
# case_insensitive
# source_file
beep.bdf
c5f9a0876e3a4d4e23883cbab1bf9b
25
# internal_option {
BLOCK_DESIGN_NAMING
OFF
}
# hierarchies {
|
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
beep_cup
# storage
db|beep.(1).cnf
db|beep.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
beep_cup.vhd
a7c599a7a3a4b333a913ddaf1f2f5f6f
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_jtag_debug_module_arbitrator
# storage
db|beep.(2).cnf
db|beep.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
beep_cup.vhd
a7c599a7a3a4b333a913ddaf1f2f5f6f
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(cpu_0_data_master_address_to_slave)
13 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_data_master_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_data_master_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_instruction_master_address_to_slave)
13 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_jtag_debug_module_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_jtag_debug_module_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_jtag_debug_module_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_jtag_debug_module_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_jtag_debug_module_writedata)
31 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_data_master_arbitrator
# storage
db|beep.(3).cnf
db|beep.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
beep_cup.vhd
a7c599a7a3a4b333a913ddaf1f2f5f6f
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(cpu_0_data_master_address)
13 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_jtag_debug_module_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(onchip_memory_0_s1_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(timer_0_s1_readdata_from_sa)
15 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_data_master_address_to_slave)
13 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_data_master_irq)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_data_master_readdata)
31 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_instruction_master_arbitrator
# storage
db|beep.(4).cnf
db|beep.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
beep_cup.vhd
a7c599a7a3a4b333a913ddaf1f2f5f6f
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(cpu_0_instruction_master_address)
13 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_jtag_debug_module_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(onchip_memory_0_s1_readdata_from_sa)
31 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_instruction_master_address_to_slave)
13 downto 0
PARAMETER_STRING
USR
 constraint(cpu_0_instruction_master_readdata)
31 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0
# storage
db|beep.(5).cnf
db|beep.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(d_irq)
31 downto 0
PARAMETER_STRING
USR
 constraint(d_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(i_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(jtag_debug_module_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(jtag_debug_module_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(jtag_debug_module_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(d_address)
13 downto 0
PARAMETER_STRING
USR
 constraint(d_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(d_writedata)
31 downto 0
PARAMETER_STRING
USR
 constraint(i_address)
13 downto 0
PARAMETER_STRING
USR
 constraint(jtag_debug_module_readdata)
31 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_test_bench
# storage
db|beep.(6).cnf
db|beep.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0_test_bench.vhd
217dd6752802995b13a7ebbe67aa284
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(d_iw)
31 downto 0
PARAMETER_STRING
USR
 constraint(d_iw_op)
5 downto 0
PARAMETER_STRING
USR
 constraint(d_iw_opx)
5 downto 0
PARAMETER_STRING
USR
 constraint(e_alu_result)
31 downto 0
PARAMETER_STRING
USR
 constraint(e_mem_byte_en)
3 downto 0
PARAMETER_STRING
USR
 constraint(e_st_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(f_pcb)
13 downto 0
PARAMETER_STRING
USR
 constraint(r_dst_regnum)
4 downto 0
PARAMETER_STRING
USR
 constraint(w_alu_result)
31 downto 0
PARAMETER_STRING
USR
 constraint(w_ienable_reg)
31 downto 0
PARAMETER_STRING
USR
 constraint(w_ipending_reg)
31 downto 0
PARAMETER_STRING
USR
 constraint(w_wr_data)
31 downto 0
PARAMETER_STRING
USR
 constraint(av_ld_data_aligned_unfiltered)
31 downto 0
PARAMETER_STRING
USR
 constraint(d_address)
13 downto 0
PARAMETER_STRING
USR
 constraint(d_byteenable)
3 downto 0
PARAMETER_STRING
USR
 constraint(i_address)
13 downto 0
PARAMETER_STRING
USR
 constraint(i_readdata)
31 downto 0
PARAMETER_STRING
USR
 constraint(av_ld_data_aligned_filtered)
31 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
cpu_0_rf_module
# storage
db|beep.(7).cnf
db|beep.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cpu_0.vhd
68d1c42abf36541c69f6a8e443c1a85
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_file
rf_ram.mif
PARAMETER_STRING
USR
 constraint(address_a)
4 downto 0
PARAMETER_STRING
USR
 constraint(address_b)
4 downto 0
PARAMETER_STRING
USR
 constraint(data_a)
31 downto 0
PARAMETER_STRING
USR
 constraint(data_b)
31 downto 0
PARAMETER_STRING
USR
 constraint(q_a)
31 downto 0
PARAMETER_STRING
USR
 constraint(q_b)
31 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera_vhdl_support.vhd
534dfcf4982d9e2da8ea40f5168a306c
}
# hierarchies {
beep_cup:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf
}
# lmf
d:|altera|72|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
altsyncram
# storage
db|beep.(8).cnf
db|beep.(8).cnf
# case_insensitive
# source_file
d:|altera|72|quartus|libraries|megafunctions|altsyncram.tdf
56e814d9f431d4c82859865aa9372
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
32
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
5
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
32
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
rf_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_b322
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1