beep.hier_info

买的开发板上自带的例程

cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~41.IN0
cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~40.IN0
cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~39.IN0
cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~38.IN0
cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~37.IN0
cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~36.IN0
cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~35.IN0
cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~34.IN0
cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~33.IN0
cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_readdata~32.IN0
cpu_0_data_master_requests_pio_beep_s1 => r_0~20.IN0
cpu_0_data_master_requests_timer_0_s1 => r_0~28.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~143.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~142.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~141.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~140.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~139.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~138.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~137.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~136.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~135.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~134.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~133.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~132.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~131.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~130.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~129.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~128.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~111.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~110.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~109.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~108.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~107.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~106.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~105.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~104.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~103.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~102.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~101.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~100.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~99.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~98.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~97.IN0
cpu_0_data_master_requests_timer_0_s1 => cpu_0_data_master_readdata~96.IN0
cpu_0_data_master_write => r_0~34.IN0
cpu_0_data_master_write => r_0~26.IN0
cpu_0_data_master_write => r_0~3.IN1
cpu_0_data_master_write => r_0~33.IN0
cpu_0_data_master_write => r_0~25.IN0
cpu_0_jtag_debug_module_readdata_from_sa[0] => cpu_0_data_master_readdata~0.IN1
cpu_0_jtag_debug_module_readdata_from_sa[1] => cpu_0_data_master_readdata~1.IN1
cpu_0_jtag_debug_module_readdata_from_sa[2] => cpu_0_data_master_readdata~2.IN1
cpu_0_jtag_debug_module_readdata_from_sa[3] => cpu_0_data_master_readdata~3.IN1
cpu_0_jtag_debug_module_readdata_from_sa[4] => cpu_0_data_master_readdata~4.IN1
cpu_0_jtag_debug_module_readdata_from_sa[5] => cpu_0_data_master_readdata~5.IN1
cpu_0_jtag_debug_module_readdata_from_sa[6] => cpu_0_data_master_readdata~6.IN1
cpu_0_jtag_debug_module_readdata_from_sa[7] => cpu_0_data_master_readdata~7.IN1
cpu_0_jtag_debug_module_readdata_from_sa[8] => cpu_0_data_master_readdata~8.IN1
cpu_0_jtag_debug_module_readdata_from_sa[9] => cpu_0_data_master_readdata~9.IN1
cpu_0_jtag_debug_module_readdata_from_sa[10] => cpu_0_data_master_readdata~10.IN1
cpu_0_jtag_debug_module_readdata_from_sa[11] => cpu_0_data_master_readdata~11.IN1
cpu_0_jtag_debug_module_readdata_from_sa[12] => cpu_0_data_master_readdata~12.IN1
cpu_0_jtag_debug_module_readdata_from_sa[13] => cpu_0_data_master_readdata~13.IN1
cpu_0_jtag_debug_module_readdata_from_sa[14] => cpu_0_data_master_readdata~14.IN1
cpu_0_jtag_debug_module_readdata_from_sa[15] => cpu_0_data_master_readdata~15.IN1
cpu_0_jtag_debug_module_readdata_from_sa[16] => cpu_0_data_master_readdata~16.IN1
cpu_0_jtag_debug_module_readdata_from_sa[17] => cpu_0_data_master_readdata~17.IN1
cpu_0_jtag_debug_module_readdata_from_sa[18] => cpu_0_data_master_readdata~18.IN1
cpu_0_jtag_debug_module_readdata_from_sa[19] => cpu_0_data_master_readdata~19.IN1
cpu_0_jtag_debug_module_readdata_from_sa[20] => cpu_0_data_master_readdata~20.IN1
cpu_0_jtag_debug_module_readdata_from_sa[21] => cpu_0_data_master_readdata~21.IN1
cpu_0_jtag_debug_module_readdata_from_sa[22] => cpu_0_data_master_readdata~22.IN1
cpu_0_jtag_debug_module_readdata_from_sa[23] => cpu_0_data_master_readdata~23.IN1
cpu_0_jtag_debug_module_readdata_from_sa[24] => cpu_0_data_master_readdata~24.IN1
cpu_0_jtag_debug_module_readdata_from_sa[25] => cpu_0_data_master_readdata~25.IN1
cpu_0_jtag_debug_module_readdata_from_sa[26] => cpu_0_data_master_readdata~26.IN1
cpu_0_jtag_debug_module_readdata_from_sa[27] => cpu_0_data_master_readdata~27.IN1
cpu_0_jtag_debug_module_readdata_from_sa[28] => cpu_0_data_master_readdata~28.IN1
cpu_0_jtag_debug_module_readdata_from_sa[29] => cpu_0_data_master_readdata~29.IN1
cpu_0_jtag_debug_module_readdata_from_sa[30] => cpu_0_data_master_readdata~30.IN1
cpu_0_jtag_debug_module_readdata_from_sa[31] => cpu_0_data_master_readdata~31.IN1
d1_cpu_0_jtag_debug_module_end_xfer => ~NO_FANOUT~
d1_onchip_memory_0_s1_end_xfer => ~NO_FANOUT~
d1_pio_beep_s1_end_xfer => ~NO_FANOUT~
d1_timer_0_s1_end_xfer => ~NO_FANOUT~
onchip_memory_0_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~32.IN1
onchip_memory_0_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~33.IN1
onchip_memory_0_s1_readdata_from_sa[2] => cpu_0_data_master_readdata~34.IN1
onchip_memory_0_s1_readdata_from_sa[3] => cpu_0_data_master_readdata~35.IN1
onchip_memory_0_s1_readdata_from_sa[4] => cpu_0_data_master_readdata~36.IN1
onchip_memory_0_s1_readdata_from_sa[5] => cpu_0_data_master_readdata~37.IN1
onchip_memory_0_s1_readdata_from_sa[6] => cpu_0_data_master_readdata~38.IN1
onchip_memory_0_s1_readdata_from_sa[7] => cpu_0_data_master_readdata~39.IN1
onchip_memory_0_s1_readdata_from_sa[8] => cpu_0_data_master_readdata~40.IN1
onchip_memory_0_s1_readdata_from_sa[9] => cpu_0_data_master_readdata~41.IN1
onchip_memory_0_s1_readdata_from_sa[10] => cpu_0_data_master_readdata~42.IN1
onchip_memory_0_s1_readdata_from_sa[11] => cpu_0_data_master_readdata~43.IN1
onchip_memory_0_s1_readdata_from_sa[12] => cpu_0_data_master_readdata~44.IN1
onchip_memory_0_s1_readdata_from_sa[13] => cpu_0_data_master_readdata~45.IN1
onchip_memory_0_s1_readdata_from_sa[14] => cpu_0_data_master_readdata~46.IN1
onchip_memory_0_s1_readdata_from_sa[15] => cpu_0_data_master_readdata~47.IN1
onchip_memory_0_s1_readdata_from_sa[16] => cpu_0_data_master_readdata~48.IN1
onchip_memory_0_s1_readdata_from_sa[17] => cpu_0_data_master_readdata~49.IN1
onchip_memory_0_s1_readdata_from_sa[18] => cpu_0_data_master_readdata~50.IN1
onchip_memory_0_s1_readdata_from_sa[19] => cpu_0_data_master_readdata~51.IN1
onchip_memory_0_s1_readdata_from_sa[20] => cpu_0_data_master_readdata~52.IN1
onchip_memory_0_s1_readdata_from_sa[21] => cpu_0_data_master_readdata~53.IN1
onchip_memory_0_s1_readdata_from_sa[22] => cpu_0_data_master_readdata~54.IN1
onchip_memory_0_s1_readdata_from_sa[23] => cpu_0_data_master_readdata~55.IN1
onchip_memory_0_s1_readdata_from_sa[24] => cpu_0_data_master_readdata~56.IN1
onchip_memory_0_s1_readdata_from_sa[25] => cpu_0_data_master_readdata~57.IN1
onchip_memory_0_s1_readdata_from_sa[26] => cpu_0_data_master_readdata~58.IN1
onchip_memory_0_s1_readdata_from_sa[27] => cpu_0_data_master_readdata~59.IN1
onchip_memory_0_s1_readdata_from_sa[28] => cpu_0_data_master_readdata~60.IN1
onchip_memory_0_s1_readdata_from_sa[29] => cpu_0_data_master_readdata~61.IN1
onchip_memory_0_s1_readdata_from_sa[30] => cpu_0_data_master_readdata~62.IN1
onchip_memory_0_s1_readdata_from_sa[31] => cpu_0_data_master_readdata~63.IN1
registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 => r_0~14.IN1
registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 => r_0~8.IN1
reset_n => internal_cpu_0_data_master_waitrequest.PRESET
timer_0_s1_irq_from_sa => cpu_0_data_master_irq[0].DATAIN
timer_0_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~96.IN1
timer_0_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~97.IN1
timer_0_s1_readdata_from_sa[2] => cpu_0_data_master_readdata~98.IN1
timer_0_s1_readdata_from_sa[3] => cpu_0_data_master_readdata~99.IN1
timer_0_s1_readdata_from_sa[4] => cpu_0_data_master_readdata~100.IN1
timer_0_s1_readdata_from_sa[5] => cpu_0_data_master_readdata~101.IN1
timer_0_s1_readdata_from_sa[6] => cpu_0_data_master_readdata~102.IN1
timer_0_s1_readdata_from_sa[7] => cpu_0_data_master_readdata~103.IN1
timer_0_s1_readdata_from_sa[8] => cpu_0_data_master_readdata~104.IN1
timer_0_s1_readdata_from_sa[9] => cpu_0_data_master_readdata~105.IN1
timer_0_s1_readdata_from_sa[10] => cpu_0_data_master_readdata~106.IN1
timer_0_s1_readdata_from_sa[11] => cpu_0_data_master_readdata~107.IN1
timer_0_s1_readdata_from_sa[12] => cpu_0_data_master_readdata~108.IN1
timer_0_s1_readdata_from_sa[13] => cpu_0_data_master_readdata~109.IN1
timer_0_s1_readdata_from_sa[14] => cpu_0_data_master_readdata~110.IN1
timer_0_s1_readdata_from_sa[15] => cpu_0_data_master_readdata~111.IN1
cpu_0_data_master_address_to_slave[0] <= cpu_0_data_master_address[0].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[1] <= cpu_0_data_master_address[1].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[2] <= cpu_0_data_master_address[2].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[3] <= cpu_0_data_master_address[3].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[4] <= cpu_0_data_master_address[4].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[5] <= cpu_0_data_master_address[5].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[6] <= cpu_0_data_master_address[6].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[7] <= cpu_0_data_master_address[7].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[8] <= cpu_0_data_master_address[8].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[9] <= cpu_0_data_master_address[9].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[10] <= cpu_0_data_master_address[10].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[11] <= cpu_0_data_master_address[11].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[12] <= cpu_0_data_master_address[12].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_address_to_slave[13] <= cpu_0_data_master_address[13].DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_irq[0] <= timer_0_s1_irq_from_sa.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_irq[1] <= <GND>
cpu_0_data_master_irq[2] <= <GND>
cpu_0_data_master_irq[3] <= <GND>
cpu_0_data_master_irq[4] <= <GND>
cpu_0_data_master_irq[5] <= <GND>
cpu_0_data_master_irq[6] <= <GND>
cpu_0_data_master_irq[7] <= <GND>
cpu_0_data_master_irq[8] <= <GND>
cpu_0_data_master_irq[9] <= <GND>
cpu_0_data_master_irq[10] <= <GND>
cpu_0_data_master_irq[11] <= <GND>
cpu_0_data_master_irq[12] <= <GND>
cpu_0_data_master_irq[13] <= <GND>
cpu_0_data_master_irq[14] <= <GND>
cpu_0_data_master_irq[15] <= <GND>
cpu_0_data_master_irq[16] <= <GND>
cpu_0_data_master_irq[17] <= <GND>
cpu_0_data_master_irq[18] <= <GND>
cpu_0_data_master_irq[19] <= <GND>
cpu_0_data_master_irq[20] <= <GND>
cpu_0_data_master_irq[21] <= <GND>
cpu_0_data_master_irq[22] <= <GND>