beep.hier_info

买的开发板上自带的例程

|beep
beep <= beep_cup:inst.out_port_from_the_pio_beep
clk => beep_cup:inst.clk
reset => beep_cup:inst.reset_n


|beep|beep_cup:inst
clk => beep_cup_reset_clk_domain_synch_module:beep_cup_reset_clk_domain_synch.clk
clk => timer_0:the_timer_0.clk
clk => timer_0_s1_arbitrator:the_timer_0_s1.clk
clk => pio_beep:the_pio_beep.clk
clk => pio_beep_s1_arbitrator:the_pio_beep_s1.clk
clk => onchip_memory_0:the_onchip_memory_0.clk
clk => onchip_memory_0_s1_arbitrator:the_onchip_memory_0_s1.clk
clk => cpu_0:the_cpu_0.jtag_debug_module_clk
clk => cpu_0:the_cpu_0.clk
clk => cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master.clk
clk => cpu_0_data_master_arbitrator:the_cpu_0_data_master.clk
clk => cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module.clk
reset_n => reset_n_sources~0.IN1
out_port_from_the_pio_beep <= pio_beep:the_pio_beep.out_port


|beep|beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module
clk => d1_reasons_to_wait.CLK
clk => cpu_0_jtag_debug_module_arb_share_counter.CLK
clk => cpu_0_jtag_debug_module_slavearbiterlockenable.CLK
clk => last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module.CLK
clk => last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module.CLK
clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[1].CLK
clk => cpu_0_jtag_debug_module_saved_chosen_master_vector[0].CLK
clk => cpu_0_jtag_debug_module_arb_addend[1].CLK
clk => cpu_0_jtag_debug_module_arb_addend[0].CLK
clk => d1_cpu_0_jtag_debug_module_end_xfer~reg0.CLK
cpu_0_data_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[1] => ~NO_FANOUT~
cpu_0_data_master_address_to_slave[2] => A_WE_StdLogicVector~17.DATAB
cpu_0_data_master_address_to_slave[3] => A_WE_StdLogicVector~16.DATAB
cpu_0_data_master_address_to_slave[4] => A_WE_StdLogicVector~15.DATAB
cpu_0_data_master_address_to_slave[5] => A_WE_StdLogicVector~14.DATAB
cpu_0_data_master_address_to_slave[6] => A_WE_StdLogicVector~13.DATAB
cpu_0_data_master_address_to_slave[7] => A_WE_StdLogicVector~12.DATAB
cpu_0_data_master_address_to_slave[8] => A_WE_StdLogicVector~11.DATAB
cpu_0_data_master_address_to_slave[9] => A_WE_StdLogicVector~10.DATAB
cpu_0_data_master_address_to_slave[10] => A_WE_StdLogicVector~9.DATAB
cpu_0_data_master_address_to_slave[11] => Equal0.IN27
cpu_0_data_master_address_to_slave[12] => Equal0.IN26
cpu_0_data_master_address_to_slave[13] => Equal0.IN25
cpu_0_data_master_byteenable[0] => A_WE_StdLogicVector~21.DATAB
cpu_0_data_master_byteenable[1] => A_WE_StdLogicVector~20.DATAB
cpu_0_data_master_byteenable[2] => A_WE_StdLogicVector~19.DATAB
cpu_0_data_master_byteenable[3] => A_WE_StdLogicVector~18.DATAB
cpu_0_data_master_debugaccess => cpu_0_jtag_debug_module_debugaccess.DATAIN
cpu_0_data_master_read => cpu_0_jtag_debug_module_in_a_read_cycle~0.IN0
cpu_0_data_master_read => internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN0
cpu_0_data_master_write => cpu_0_jtag_debug_module_in_a_write_cycle.IN0
cpu_0_data_master_write => cpu_0_jtag_debug_module_write~0.IN0
cpu_0_data_master_write => internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module~0.IN1
cpu_0_data_master_writedata[0] => cpu_0_jtag_debug_module_writedata[0].DATAIN
cpu_0_data_master_writedata[1] => cpu_0_jtag_debug_module_writedata[1].DATAIN
cpu_0_data_master_writedata[2] => cpu_0_jtag_debug_module_writedata[2].DATAIN
cpu_0_data_master_writedata[3] => cpu_0_jtag_debug_module_writedata[3].DATAIN
cpu_0_data_master_writedata[4] => cpu_0_jtag_debug_module_writedata[4].DATAIN
cpu_0_data_master_writedata[5] => cpu_0_jtag_debug_module_writedata[5].DATAIN
cpu_0_data_master_writedata[6] => cpu_0_jtag_debug_module_writedata[6].DATAIN
cpu_0_data_master_writedata[7] => cpu_0_jtag_debug_module_writedata[7].DATAIN
cpu_0_data_master_writedata[8] => cpu_0_jtag_debug_module_writedata[8].DATAIN
cpu_0_data_master_writedata[9] => cpu_0_jtag_debug_module_writedata[9].DATAIN
cpu_0_data_master_writedata[10] => cpu_0_jtag_debug_module_writedata[10].DATAIN
cpu_0_data_master_writedata[11] => cpu_0_jtag_debug_module_writedata[11].DATAIN
cpu_0_data_master_writedata[12] => cpu_0_jtag_debug_module_writedata[12].DATAIN
cpu_0_data_master_writedata[13] => cpu_0_jtag_debug_module_writedata[13].DATAIN
cpu_0_data_master_writedata[14] => cpu_0_jtag_debug_module_writedata[14].DATAIN
cpu_0_data_master_writedata[15] => cpu_0_jtag_debug_module_writedata[15].DATAIN
cpu_0_data_master_writedata[16] => cpu_0_jtag_debug_module_writedata[16].DATAIN
cpu_0_data_master_writedata[17] => cpu_0_jtag_debug_module_writedata[17].DATAIN
cpu_0_data_master_writedata[18] => cpu_0_jtag_debug_module_writedata[18].DATAIN
cpu_0_data_master_writedata[19] => cpu_0_jtag_debug_module_writedata[19].DATAIN
cpu_0_data_master_writedata[20] => cpu_0_jtag_debug_module_writedata[20].DATAIN
cpu_0_data_master_writedata[21] => cpu_0_jtag_debug_module_writedata[21].DATAIN
cpu_0_data_master_writedata[22] => cpu_0_jtag_debug_module_writedata[22].DATAIN
cpu_0_data_master_writedata[23] => cpu_0_jtag_debug_module_writedata[23].DATAIN
cpu_0_data_master_writedata[24] => cpu_0_jtag_debug_module_writedata[24].DATAIN
cpu_0_data_master_writedata[25] => cpu_0_jtag_debug_module_writedata[25].DATAIN
cpu_0_data_master_writedata[26] => cpu_0_jtag_debug_module_writedata[26].DATAIN
cpu_0_data_master_writedata[27] => cpu_0_jtag_debug_module_writedata[27].DATAIN
cpu_0_data_master_writedata[28] => cpu_0_jtag_debug_module_writedata[28].DATAIN
cpu_0_data_master_writedata[29] => cpu_0_jtag_debug_module_writedata[29].DATAIN
cpu_0_data_master_writedata[30] => cpu_0_jtag_debug_module_writedata[30].DATAIN
cpu_0_data_master_writedata[31] => cpu_0_jtag_debug_module_writedata[31].DATAIN
cpu_0_instruction_master_address_to_slave[0] => ~NO_FANOUT~
cpu_0_instruction_master_address_to_slave[1] => ~NO_FANOUT~
cpu_0_instruction_master_address_to_slave[2] => A_WE_StdLogicVector~17.DATAA
cpu_0_instruction_master_address_to_slave[3] => A_WE_StdLogicVector~16.DATAA
cpu_0_instruction_master_address_to_slave[4] => A_WE_StdLogicVector~15.DATAA
cpu_0_instruction_master_address_to_slave[5] => A_WE_StdLogicVector~14.DATAA
cpu_0_instruction_master_address_to_slave[6] => A_WE_StdLogicVector~13.DATAA
cpu_0_instruction_master_address_to_slave[7] => A_WE_StdLogicVector~12.DATAA
cpu_0_instruction_master_address_to_slave[8] => A_WE_StdLogicVector~11.DATAA
cpu_0_instruction_master_address_to_slave[9] => A_WE_StdLogicVector~10.DATAA
cpu_0_instruction_master_address_to_slave[10] => A_WE_StdLogicVector~9.DATAA
cpu_0_instruction_master_address_to_slave[11] => Equal1.IN27
cpu_0_instruction_master_address_to_slave[12] => Equal1.IN26
cpu_0_instruction_master_address_to_slave[13] => Equal1.IN25
cpu_0_instruction_master_read => cpu_0_jtag_debug_module_in_a_read_cycle~1.IN0
cpu_0_instruction_master_read => internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~1.IN0
cpu_0_instruction_master_read => internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~0.IN0
cpu_0_jtag_debug_module_readdata[0] => cpu_0_jtag_debug_module_readdata_from_sa[0].DATAIN
cpu_0_jtag_debug_module_readdata[1] => cpu_0_jtag_debug_module_readdata_from_sa[1].DATAIN
cpu_0_jtag_debug_module_readdata[2] => cpu_0_jtag_debug_module_readdata_from_sa[2].DATAIN
cpu_0_jtag_debug_module_readdata[3] => cpu_0_jtag_debug_module_readdata_from_sa[3].DATAIN
cpu_0_jtag_debug_module_readdata[4] => cpu_0_jtag_debug_module_readdata_from_sa[4].DATAIN
cpu_0_jtag_debug_module_readdata[5] => cpu_0_jtag_debug_module_readdata_from_sa[5].DATAIN
cpu_0_jtag_debug_module_readdata[6] => cpu_0_jtag_debug_module_readdata_from_sa[6].DATAIN
cpu_0_jtag_debug_module_readdata[7] => cpu_0_jtag_debug_module_readdata_from_sa[7].DATAIN
cpu_0_jtag_debug_module_readdata[8] => cpu_0_jtag_debug_module_readdata_from_sa[8].DATAIN
cpu_0_jtag_debug_module_readdata[9] => cpu_0_jtag_debug_module_readdata_from_sa[9].DATAIN
cpu_0_jtag_debug_module_readdata[10] => cpu_0_jtag_debug_module_readdata_from_sa[10].DATAIN
cpu_0_jtag_debug_module_readdata[11] => cpu_0_jtag_debug_module_readdata_from_sa[11].DATAIN
cpu_0_jtag_debug_module_readdata[12] => cpu_0_jtag_debug_module_readdata_from_sa[12].DATAIN
cpu_0_jtag_debug_module_readdata[13] => cpu_0_jtag_debug_module_readdata_from_sa[13].DATAIN
cpu_0_jtag_debug_module_readdata[14] => cpu_0_jtag_debug_module_readdata_from_sa[14].DATAIN
cpu_0_jtag_debug_module_readdata[15] => cpu_0_jtag_debug_module_readdata_from_sa[15].DATAIN
cpu_0_jtag_debug_module_readdata[16] => cpu_0_jtag_debug_module_readdata_from_sa[16].DATAIN
cpu_0_jtag_debug_module_readdata[17] => cpu_0_jtag_debug_module_readdata_from_sa[17].DATAIN
cpu_0_jtag_debug_module_readdata[18] => cpu_0_jtag_debug_module_readdata_from_sa[18].DATAIN
cpu_0_jtag_debug_module_readdata[19] => cpu_0_jtag_debug_module_readdata_from_sa[19].DATAIN
cpu_0_jtag_debug_module_readdata[20] => cpu_0_jtag_debug_module_readdata_from_sa[20].DATAIN
cpu_0_jtag_debug_module_readdata[21] => cpu_0_jtag_debug_module_readdata_from_sa[21].DATAIN
cpu_0_jtag_debug_module_readdata[22] => cpu_0_jtag_debug_module_readdata_from_sa[22].DATAIN
cpu_0_jtag_debug_module_readdata[23] => cpu_0_jtag_debug_module_readdata_from_sa[23].DATAIN
cpu_0_jtag_debug_module_readdata[24] => cpu_0_jtag_debug_module_readdata_from_sa[24].DATAIN
cpu_0_jtag_debug_module_readdata[25] => cpu_0_jtag_debug_module_readdata_from_sa[25].DATAIN
cpu_0_jtag_debug_module_readdata[26] => cpu_0_jtag_debug_module_readdata_from_sa[26].DATAIN
cpu_0_jtag_debug_module_readdata[27] => cpu_0_jtag_debug_module_readdata_from_sa[27].DATAIN
cpu_0_jtag_debug_module_readdata[28] => cpu_0_jtag_debug_module_readdata_from_sa[28].DATAIN
cpu_0_jtag_debug_module_readdata[29] => cpu_0_jtag_debug_module_readdata_from_sa[29].DATAIN
cpu_0_jtag_debug_module_readdata[30] => cpu_0_jtag_debug_module_readdata_from_sa[30].DATAIN
cpu_0_jtag_debug_module_readdata[31] => cpu_0_jtag_debug_module_readdata_from_sa[31].DATAIN
cpu_0_jtag_debug_module_resetrequest => cpu_0_jtag_debug_module_resetrequest_from_sa.DATAIN
reset_n => cpu_0_jtag_debug_module_reset_n.DATAIN
reset_n => cpu_0_jtag_debug_module_arb_addend[0].PRESET
reset_n => cpu_0_jtag_debug_module_arb_addend[1].ACLR
reset_n => cpu_0_jtag_debug_module_saved_chosen_master_vector[0].ACLR
reset_n => cpu_0_jtag_debug_module_saved_chosen_master_vector[1].ACLR
reset_n => last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module.ACLR
reset_n => last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module.ACLR
reset_n => cpu_0_jtag_debug_module_slavearbiterlockenable.ACLR
reset_n => cpu_0_jtag_debug_module_arb_share_counter.ACLR
reset_n => d1_reasons_to_wait.ACLR
reset_n => d1_cpu_0_jtag_debug_module_end_xfer~reg0.PRESET
reset_n => cpu_0_jtag_debug_module_reset.DATAIN
cpu_0_data_master_granted_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_grant_vector~0.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module <= internal_cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module~0.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module <= <GND>
cpu_0_data_master_requests_cpu_0_jtag_debug_module <= internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module~1.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_instruction_master_granted_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_grant_vector~1.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module <= internal_cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module~0.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module <= <GND>
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module <= internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~1.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_address[0] <= A_WE_StdLogicVector~17.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_address[1] <= A_WE_StdLogicVector~16.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_address[2] <= A_WE_StdLogicVector~15.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_address[3] <= A_WE_StdLogicVector~14.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_address[4] <= A_WE_StdLogicVector~13.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_address[5] <= A_WE_StdLogicVector~12.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_address[6] <= A_WE_StdLogicVector~11.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_address[7] <= A_WE_StdLogicVector~10.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_address[8] <= A_WE_StdLogicVector~9.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_begintransfer <= cpu_0_jtag_debug_module_begins_xfer~1.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_byteenable[0] <= A_WE_StdLogicVector~21.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_byteenable[1] <= A_WE_StdLogicVector~20.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_byteenable[2] <= A_WE_StdLogicVector~19.DB_MAX_OUTPUT_PORT_TYPE
cpu_0_jtag_debug_module_byteenable[3] <= A_WE_StdLogicVector~18.DB_MAX_OUTPUT_PORT_TYPE