beep.fit.qmsg

买的开发板上自带的例程

{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Info: Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.826 ns register register " "Info: Estimated most critical path is register to register delay of 9.826 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns beep_cup:inst\|cpu_0:the_cpu_0\|F_pc\[10\] 1 REG LAB_X15_Y8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y8; Fanout = 4; REG Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|F_pc\[10\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { beep_cup:inst|cpu_0:the_cpu_0|F_pc[10] } "NODE_NAME" } } { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 4792 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.511 ns) + CELL(0.370 ns) 0.881 ns beep_cup:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~198 2 COMB LAB_X15_Y8 40 " "Info: 2: + IC(0.511 ns) + CELL(0.370 ns) = 0.881 ns; Loc. = LAB_X15_Y8; Fanout = 40; COMB Node = 'beep_cup:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~198'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.881 ns" { beep_cup:inst|cpu_0:the_cpu_0|F_pc[10] beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~198 } "NODE_NAME" } } { "beep_cup.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/beep_cup.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.206 ns) 2.781 ns beep_cup:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_data_master_granted_cpu_0_jtag_debug_module~60 3 COMB LAB_X18_Y6 19 " "Info: 3: + IC(1.694 ns) + CELL(0.206 ns) = 2.781 ns; Loc. = LAB_X18_Y6; Fanout = 19; COMB Node = 'beep_cup:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_data_master_granted_cpu_0_jtag_debug_module~60'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~198 beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_data_master_granted_cpu_0_jtag_debug_module~60 } "NODE_NAME" } } { "beep_cup.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/beep_cup.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.276 ns) + CELL(0.206 ns) 4.263 ns beep_cup:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_address\[5\]~121 4 COMB LAB_X15_Y6 33 " "Info: 4: + IC(1.276 ns) + CELL(0.206 ns) = 4.263 ns; Loc. = LAB_X15_Y6; Fanout = 33; COMB Node = 'beep_cup:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_address\[5\]~121'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.482 ns" { beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_data_master_granted_cpu_0_jtag_debug_module~60 beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[5]~121 } "NODE_NAME" } } { "beep_cup.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/beep_cup.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.276 ns) + CELL(0.202 ns) 5.741 ns beep_cup:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg\|Equal0~71 5 COMB LAB_X18_Y6 26 " "Info: 5: + IC(1.276 ns) + CELL(0.202 ns) = 5.741 ns; Loc. = LAB_X18_Y6; Fanout = 26; COMB Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg\|Equal0~71'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.478 ns" { beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[5]~121 beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal0~71 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 6.552 ns beep_cup:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg\|Equal1~34 6 COMB LAB_X18_Y6 19 " "Info: 6: + IC(0.605 ns) + CELL(0.206 ns) = 6.552 ns; Loc. = LAB_X18_Y6; Fanout = 19; COMB Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg\|Equal1~34'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal0~71 beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal1~34 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.894 ns) + CELL(0.651 ns) 8.097 ns beep_cup:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[16\]~1128 7 COMB LAB_X18_Y3 1 " "Info: 7: + IC(0.894 ns) + CELL(0.651 ns) = 8.097 ns; Loc. = LAB_X18_Y3; Fanout = 1; COMB Node = 'beep_cup:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[16\]~1128'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.545 ns" { beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal1~34 beep_cup:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~1128 } "NODE_NAME" } } { "beep_cup.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/beep_cup.vhd" 408 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.650 ns) 8.907 ns beep_cup:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[16\]~1129 8 COMB LAB_X18_Y3 1 " "Info: 8: + IC(0.160 ns) + CELL(0.650 ns) = 8.907 ns; Loc. = LAB_X18_Y3; Fanout = 1; COMB Node = 'beep_cup:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[16\]~1129'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { beep_cup:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~1128 beep_cup:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~1129 } "NODE_NAME" } } { "beep_cup.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/beep_cup.vhd" 408 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.651 ns) 9.718 ns beep_cup:inst\|cpu_0:the_cpu_0\|av_ld_byte2_data\[0\]~16 9 COMB LAB_X18_Y3 1 " "Info: 9: + IC(0.160 ns) + CELL(0.651 ns) = 9.718 ns; Loc. = LAB_X18_Y3; Fanout = 1; COMB Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|av_ld_byte2_data\[0\]~16'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { beep_cup:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~1129 beep_cup:inst|cpu_0:the_cpu_0|av_ld_byte2_data[0]~16 } "NODE_NAME" } } { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 5217 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.826 ns beep_cup:inst\|cpu_0:the_cpu_0\|av_ld_byte2_data\[0\] 10 REG LAB_X18_Y3 2 " "Info: 10: + IC(0.000 ns) + CELL(0.108 ns) = 9.826 ns; Loc. = LAB_X18_Y3; Fanout = 2; REG Node = 'beep_cup:inst\|cpu_0:the_cpu_0\|av_ld_byte2_data\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { beep_cup:inst|cpu_0:the_cpu_0|av_ld_byte2_data[0]~16 beep_cup:inst|cpu_0:the_cpu_0|av_ld_byte2_data[0] } "NODE_NAME" } } { "cpu_0.vhd" "" { Text "F:/alter/2sfenpin/liz/beep_2c5/cpu_0.vhd" 5217 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.250 ns ( 33.08 % ) " "Info: Total cell delay = 3.250 ns ( 33.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.576 ns ( 66.92 % ) " "Info: Total interconnect delay = 6.576 ns ( 66.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.826 ns" { beep_cup:inst|cpu_0:the_cpu_0|F_pc[10] beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_instruction_master_requests_cpu_0_jtag_debug_module~198 beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_data_master_granted_cpu_0_jtag_debug_module~60 beep_cup:inst|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_address[5]~121 beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal0~71 beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|Equal1~34 beep_cup:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~1128 beep_cup:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~1129 beep_cup:inst|cpu_0:the_cpu_0|av_ld_byte2_data[0]~16 beep_cup:inst|cpu_0:the_cpu_0|av_ld_byte2_data[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Info: Average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X14_Y0 X28_Y14 " "Info: Peak interconnect usage is 15% of the available device resources in the region that extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:11 " "Info: Fitter routing operations ending: elapsed time is 00:00:11" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}