beep.map.rpt

买的开发板上自带的例程

Analysis & Synthesis report for beep
Fri Nov 21 19:24:52 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Registers Protected by Synthesis
  9. Registers Removed During Synthesis
 10. Removed Registers Triggering Further Register Optimizations
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for beep_cup:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_b322:auto_generated
 15. Source assignments for beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated
 16. Source assignments for beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated
 17. Source assignments for beep_cup:inst|onchip_memory_0:the_onchip_memory_0|altsyncram:the_altsyncram|altsyncram_28a1:auto_generated
 18. Source assignments for beep_cup:inst|beep_cup_reset_clk_domain_synch_module:beep_cup_reset_clk_domain_synch
 19. Source assignments for sld_hub:sld_hub_inst
 20. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 21. Parameter Settings for User Entity Instance: beep_cup:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf
 22. Parameter Settings for User Entity Instance: beep_cup:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram
 23. Parameter Settings for User Entity Instance: beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
 24. Parameter Settings for User Entity Instance: beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 25. Parameter Settings for User Entity Instance: beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
 26. Parameter Settings for User Entity Instance: beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 27. Parameter Settings for User Entity Instance: beep_cup:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1
 28. Parameter Settings for User Entity Instance: beep_cup:inst|onchip_memory_0:the_onchip_memory_0|altsyncram:the_altsyncram
 29. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 30. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri Nov 21 19:24:52 2008    ;
; Quartus II Version                 ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name                      ; beep                                     ;
; Top-level Entity Name              ; beep                                     ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 1,169                                    ;
;     Total combinational functions  ; 1,169                                    ;
;     Dedicated logic registers      ; 669                                      ;
; Total registers                    ; 669                                      ;
; Total pins                         ; 7                                        ;