arm.isa

arm的模拟器

	}
	if ($wfld$)
			WRITE_REG($rn$, address);
	WRITE_REG($rd$, rslt16);
"
}

op ld2_imm_s(----0000:ufld:1:-:1:rn:rd:imm4_1:1101:imm4_2)
{
execute="
	offset = ($imm4_1$ << 4) | $imm4_2$;

	address = READ_REG($rn$);
	
	MMU_READ_BYTE(address,&rslt8);
	if(fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
	WRITE_REG($rd$, (int8_t)rslt8);
"
}

op ld2_imm_ps(----0001:ufld:1:wfld:1:rn:rd:imm4_1:1101:imm4_2)
{
execute="
	offset = ($imm4_1$ << 4) | $imm4_2$;

	address = $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset;

	MMU_READ_BYTE(address,&rslt8);
	if(fault){
		ABORT( DataAbortV );
	}
	if ($wfld$)
		WRITE_REG($rn$, address);

	WRITE_REG($rd$, (int8_t)rslt8);
"
}


op ld2_imm_hs(----0000:ufld:1:-:1:rn:rd:imm4_1:1111:imm4_2)
{
execute="
	offset = ($imm4_1$ << 4) | $imm4_2$;

	address = READ_REG($rn$);

	MMU_READ_HALF_WORD(address,&rslt16);
	if(fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
	WRITE_REG($rd$, (int16_t)rslt16);

"
}

op ld2_imm_phs(----0001:ufld:1:wfld:1:rn:rd:imm4_1:1111:imm4_2)
{
execute="
	offset = ($imm4_1$ << 4) | $imm4_2$;

	address = $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset;

	MMU_READ_HALF_WORD(address,&rslt16);
	if(fault){
		ABORT( DataAbortV );
	}
	if ($wfld$)
		WRITE_REG($rn$, address);
	WRITE_REG($rd$, (int16_t)rslt16);
"
}

op ld2_reg_h(----0000:ufld:0:-:1:rn:rd:0000:1011:rm)
{
execute="
	offset = READ_REG($rm$);
	address = READ_REG($rn$);

	MMU_READ_HALF_WORD(address,&rslt16);
	if(fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
	WRITE_REG($rd$, rslt16);
"
}

op ld2_reg_ph(----0001:ufld:0:wfld:1:rn:rd:0000:1011:rm)
{
execute="
	offset = READ_REG($rm$);
	address = $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset;


	MMU_READ_HALF_WORD(address,&rslt16);
	if(fault){
		ABORT( DataAbortV );
	}
	if ($wfld$)
		WRITE_REG($rn$, address);
	WRITE_REG($rd$, rslt16);
"
}

op ld2_reg_s(----0000:ufld:0:-:1:rn:rd:0000:1101:rm)
{
execute="
	offset = READ_REG($rm$);
	address = READ_REG($rn$);
	
	MMU_READ_BYTE(address,&rslt8);
	if(fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
	WRITE_REG($rd$, (int8_t)rslt8);
"
}

op ld2_reg_ps(----0001:ufld:0:wfld:1:rn:rd:0000:1101:rm)
{
execute="
	offset = READ_REG($rm$);
	address = $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset;

	MMU_READ_BYTE(address,&rslt8);
	if(fault){
		ABORT( DataAbortV );
	}
	if ($wfld$)
		WRITE_REG($rn$, address);
	WRITE_REG($rd$, (int8_t)rslt8);
"
}

op ld2_reg_hs(----0000:ufld:0:-:1:rn:rd:0000:1111:rm)
{
execute="
	offset = READ_REG($rm$);
	address = READ_REG($rn$);

	MMU_READ_HALF_WORD(address,&rslt16);
	if(fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
	WRITE_REG($rd$, (int16_t)rslt16);
"
}

op ld2_reg_phs(----0001:ufld:0:wfld:1:rn:rd:0000:1111:rm)
{
execute="
	offset = READ_REG($rm$);

	address = $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset;

	MMU_READ_HALF_WORD(address,&rslt16);
	if(fault){
		ABORT( DataAbortV );
	}
	if ($wfld$)
		WRITE_REG($rn$, address);
	WRITE_REG($rd$, (int16_t)rslt16);
"
}

op stt_imm(----0100:ufld:010:rn:rd:imm12)
{
execute="
	address = READ_REG($rn$);
	current_mode = TRANSLATION_MODE(USR_MODE);

	MMU_WRITE_WORD(address, READ_REG($rd$));
	TRANSLATION_MODE(current_mode);

	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+$imm12$:READ_REG($rn$)-$imm12$);
"
}

op stt_imm_b(----0100:ufld:110:rn:rd:imm12)
{
execute="
	address = READ_REG($rn$);
	current_mode = TRANSLATION_MODE(USR_MODE);
	
	MMU_WRITE_BYTE(address, READ_REG($rd$));
	TRANSLATION_MODE(current_mode);

	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+$imm12$:READ_REG($rn$)-$imm12$);
"
}

op stt_reg(----0110:ufld:010:rn:rd:imm_shifts)
{
execute="
    offset = $imm_shifts$;
	address = READ_REG($rn$);
	current_mode = TRANSLATION_MODE(USR_MODE);

	MMU_WRITE_WORD(address, READ_REG($rd$));
	TRANSLATION_MODE(current_mode);

	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
"
}

op stt_reg_b(----0110:ufld:110:rn:rd:imm_shifts)
{
execute="
    offset = $imm_shifts$;
	address = READ_REG($rn$);
	current_mode = TRANSLATION_MODE(USR_MODE);

	MMU_WRITE_BYTE(address, READ_REG($rd$));
	TRANSLATION_MODE(current_mode);

	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
"
}

op st1_imm(----0100:ufld:000:rn:rd:imm12)
{
execute="
	address = READ_REG($rn$);
	MMU_WRITE_WORD(address, READ_REG($rd$));

	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+$imm12$:READ_REG($rn$)-$imm12$);
"
}

op st1_imm_p(----0101:ufld:0:wfld:0:rn:rd:imm12)
{
execute="
	address = $ufld$?READ_REG($rn$)+$imm12$:READ_REG($rn$)-$imm12$;
	MMU_WRITE_WORD(address, READ_REG($rd$));

	if (fault){
		ABORT( DataAbortV );
	}
	if($wfld$)
		WRITE_REG($rn$, address);
"
}

op st1_imm_b(----0100:ufld:100:rn:rd:imm12)
{
execute="
	address = READ_REG($rn$);
	MMU_WRITE_BYTE(address, READ_REG($rd$));

	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+$imm12$:READ_REG($rn$)-$imm12$);
"
}

op st1_imm_pb(----0101:ufld:1:wfld:0:rn:rd:imm12)
{
execute="
	address = $ufld$?READ_REG($rn$)+$imm12$:READ_REG($rn$)-$imm12$;
	MMU_WRITE_BYTE(address, READ_REG($rd$));
	if (fault){
		ABORT( DataAbortV );
	}
	if($wfld$)
		WRITE_REG($rn$, address);
"
}

op st1_reg(----0110:ufld:000:rn:rd:imm_shifts)
{
execute="
    offset = $imm_shifts$;
	address = READ_REG($rn$);

	MMU_WRITE_WORD(address, READ_REG($rd$));
	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
"
}

op st1_reg_p(----0111:ufld:0:wfld:0:rn:rd:imm_shifts)
{
execute="
    offset = $imm_shifts$;
	address = $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset;

	MMU_WRITE_WORD(address, READ_REG($rd$));
	if (fault){
		ABORT( DataAbortV );
	}
	if($wfld$)
		WRITE_REG($rn$, address);
"
}

op st1_reg_b(----0110:ufld:100:rn:rd:imm_shifts)
{
execute="
    offset = $imm_shifts$;
	address = READ_REG($rn$);

	MMU_WRITE_BYTE(address, READ_REG($rd$));
	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
"
}

op st1_reg_pb(----0111:ufld:1:wfld:0:rn:rd:imm_shifts)
{
execute="
    offset = $imm_shifts$;
	address = $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset;

	MMU_WRITE_BYTE(address, READ_REG($rd$));
	if (fault){
		ABORT( DataAbortV );
	}
	if($wfld$)
		WRITE_REG($rn$, address);
"
}

op st2_imm(----0000:ufld:1-0:rn:rd:imm4_1:1011:imm4_2)
{
execute="
	offset = ($imm4_1$ << 4) | $imm4_2$;
	address = READ_REG($rn$);

	MMU_WRITE_HALF_WORD(address, READ_REG($rd$));
	
	if (fault){
		ABORT( DataAbortV );
	}

	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
"
}

op st2_imm_p(----0001:ufld:1:wfld:0:rn:rd:imm4_1:1011:imm4_2)
{
execute="
	offset = ($imm4_1$ << 4) | $imm4_2$;
	address = $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset;

	MMU_WRITE_HALF_WORD(address, READ_REG($rd$));

	if (fault){
		ABORT( DataAbortV );
	}
	if ($wfld$)
		WRITE_REG($rn$, address);
"
}

op st2_reg(----0000:ufld:0-0:rn:rd:00001011:rm)
{
execute="
	offset = READ_REG($rm$);
	address = READ_REG($rn$);

	MMU_WRITE_HALF_WORD(address, READ_REG($rd$));
	
	if (fault){
		ABORT( DataAbortV );
	}

	WRITE_REG($rn$, $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset);
"
}

op st2_reg_p(----0001:ufld:0:wfld:0:rn:rd:00001011:rm)
{
execute="
	offset = READ_REG($rm$);
	address = $ufld$?READ_REG($rn$)+offset:READ_REG($rn$)-offset;

	MMU_WRITE_HALF_WORD(address, READ_REG($rd$));

	if (fault){
		ABORT( DataAbortV );
	}

	if ($wfld$)
		WRITE_REG($rn$, address);
"
}

op swap(----00010000:rn:rd:0000:1001:rm)
{
execute="
	address = READ_REG($rn$);
	MMU_READ_WORD(address,&rslt32);
	if (fault){
		ABORT( DataAbortV );
	}
	MMU_WRITE_WORD(address, READ_REG($rm$));
	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rd$,rslt32);
"
}

op swap_byte(----00010100:rn:rd:0000:1001:rm)
{
execute="
	address = READ_REG($rn$);
	MMU_READ_BYTE(address,&rslt8);
	if(fault){
		ABORT( DataAbortV );
	}
	MMU_WRITE_BYTE(address, (uint8_t)READ_REG($rm$));
	if (fault){
		ABORT( DataAbortV );
	}
	WRITE_REG($rd$, (uint32_t)rslt8);
"
}



op ldm1(----100:ldm_mode1:reg_mask)
{
execute="
	pcount = popcount16($reg_mask$)*4;
	
	$ldm_mode1$
	
	address = start_addr-(start_addr&0x3);
	iterator = rmo16($reg_mask$);
	while (iterator<16) {
		if ($reg_mask$&(1<<iterator)) {
			MMU_READ_WORD(address, &val32);
			if(fault){
				WRITE_REG(($inst$>>16)&0xF, base_addr);
				XSCALE_UPDATE_FSR_FAR(ARMul_CP15_R5_ST_ALIGN,address);
				ABORT( DataAbortV );
			}
			WRITE_REG(iterator, val32);
			address += 4;
		}
		iterator++;
	}

"
}

op ldm2(----100:ldm_mode2:0:reg_mask2)
{
execute="
	pcount = popcount16($reg_mask2$)*4;
	$ldm_mode2$

	address = start_addr-(start_addr&0x3);
	current_mode = CPU_MODE;
	SWITCH_BANK(current_mode,USR_MODE);	

	iterator = rmo16($reg_mask2$);
	while (iterator<15) {
		if ($reg_mask2$&(1<<iterator)) {
			MMU_READ_WORD(address,&val32);
			if(fault){
				SWITCH_BANK(USR_MODE,current_mode);
				WRITE_REG(($inst$>>16)&0xF, base_addr);
				XSCALE_UPDATE_FSR_FAR(ARMul_CP15_R5_ST_ALIGN,address);
				ABORT( DataAbortV );
			}
			WRITE_REG(iterator, val32);
			address += 4;
		}
		iterator++;
	}

	SWITCH_BANK(USR_MODE,current_mode);	

"
}
op ldm3(----100:ldm_mode3:1:reg_mask2)
{
execute="

	pcount = popcount16($reg_mask2$)*4 + 4;
	$ldm_mode3$

	address = start_addr-(start_addr&0x3);
	iterator = rmo16($reg_mask2$);
	while (iterator<15) {
		if ($reg_mask2$&(1<<iterator)) {
			MMU_READ_WORD(address,&val32);
			if(fault){
				WRITE_REG(($inst$>>16)&0xF, base_addr);
				XSCALE_UPDATE_FSR_FAR(ARMul_CP15_R5_ST_ALIGN,address);
				ABORT( DataAbortV );
			}
			WRITE_REG(iterator, val32);
			address += 4;
		}
		iterator++;
	}

	WRITE_CPSR(SPSR);
	MMU_READ_WORD(address,&val32);
	if(fault){
		WRITE_REG(($inst$>>16)&0xF, base_addr);
		XSCALE_UPDATE_FSR_FAR(ARMul_CP15_R5_ST_ALIGN,address);
		ABORT( DataAbortV );
	}

	WRITE_REG(15, val32);


"
}

op stm1(----100:stm_mode1:reg_mask)
{
execute="
	pcount = popcount16($reg_mask$)*4;

	$stm_mode1$

	address = start_addr - (start_addr&0x3);

	/* This is not perfect exception here since
	   write may have been committed before exception occurs. */
	iterator = rmo16($reg_mask$);
	while (iterator<16) {
		if ($reg_mask$&(1<<iterator)) {
			MMU_WRITE_WORD(address, READ_REG(iterator));
			if (fault){
				WRITE_REG(($inst$>>16)&0xF, base_addr);
				XSCALE_UPDATE_FSR_FAR(ARMul_CP15_R5_ST_ALIGN,address);
				ABORT( DataAbortV );
			}
			address += 4;
		}
		iterator++;
	}

"
}

op stm2(----100:stm_mode2:reg_mask)
{
execute="
	pcount = popcount16($reg_mask$)*4;

	$stm_mode2$

	address = start_addr - (start_addr&0x3);
	current_mode = CPU_MODE;
	SWITCH_BANK(current_mode,USR_MODE);

	/* This is not perfect exception here since
	   write may have been committed before exception occurs. */
	iterator = rmo16($reg_mask$);
	while (iterator<16) {
		if ($reg_mask$&(1<<iterator)) {
			MMU_WRITE_WORD(address, READ_REG(iterator));
			if (fault){
				SWITCH_BANK(USR_MODE,current_mode);
				WRITE_REG(($inst$>>16)&0xF, base_addr);
				XSCALE_UPDATE_FSR_FAR(ARMul_CP15_R5_ST_ALIGN,address);
				ABORT( DataAbortV );
			}
			address += 4;
		}
		iterator++;
	}
	SWITCH_BANK(USR_MODE,current_mode);

"
}


op branch(----1010:imm24) {
ctarget="$pc$+((int32_t)($imm24$<<8)>>6)"
}

op branch_exchange(----00010010:1111:1111:1111:0001:rm) {
execute="
	if (READ_REG($rm$) & 1){
		ABORT2(UndefinedInstrV);
	}
	WRITE_REG(15, READ_REG($rm$) & 0xFFFFFFFC);
"
}

op branch_link(----1011:imm24) {
execute="
	WRITE_REG(LRIND, $pc$-4);
"
ctarget="$pc$+((int32_t)($imm24$<<8)>>6)"
}

op mrs(----000100001111:rd:000000000000) {
execute="
    WRITE_REG($rd$, CPSR);
"
}

op mrs_r(----000101001111:rd:000000000000) {
execute="
    WRITE_REG($rd$, SPSR);
"
}

op msri(----00110010:field_mask:1111:rotate_imm32) {
execute="
    rslt32 = $rotate_imm32$;
    UPDATE_CPSR(rslt32, $field_mask$);
"
}

op msri_r(----00110110:field_mask:1111:rotate_imm32) {
execute="
    rslt32 = $rotate_imm32$;
    UPDATE_SPSR(rslt32, $field_mask$);
"
}

op msr(----00010010:field_mask:111100000000:rm) {
execute="
    UPDATE_CPSR(READ_REG($rm$), $field_mask$);
"
}

op msr_r(----00010110:field_mask:111100000000:rm) {
execute="
    UPDATE_SPSR(READ_REG($rm$), $field_mask$);
"
}

op sc(----1111------------------------) {
execute="
	if ($inst$ == ABORTWORD && emu->abort_addr == ($pc$-8) ) {
		/* A prefetch abort.  */
		XSCALE_UPDATE_FSR_FAR(ARMul_CP15_R5_MMU_EXCPT, $pc$-8);
		ABORT2(PrefetchAbortV);
	}

	DO_SWI($inst$);
"
}

op cdp(----1110:----:----:----:cp_num:---0:----){
execute="
		
	if (emu->copro[$cp_num$] == NULL){
		ABORT2(UndefinedInstrV);
	}

	if (!CP_ACCESS_ALLOWED ($cp_num$)) {
		ABORT2(UndefinedInstrV);
	}

	
	cpab = emu->copro[$cp_num$]->CDP(ARMul_FIRST, $inst$);
	while (cpab == ARMul_BUSY) {
		if (emu->int_pending ()) {
			cpab = emu->copro[$cp_num$]->CDP(ARMul_INTERRUPT, $inst$);
		}
		else
			cpab = emu->copro[$cp_num$]->CDP(ARMul_BUSY, $inst$);
	}


	if (cpab == ARMul_CANT){
		ABORT2(UndefinedInstrV);
	}

"
}

op mcr(----1110:---0:----:rd:cp_num:---1:----){
execute="

	if (emu->copro[$cp_num$] == NULL){
		ABORT2(UndefinedInstrV);
	}

	if (!CP_ACCESS_ALLOWED ($cp_num$)) {
		ABORT2(UndefinedInstrV);
	}
	
	cpab = emu->copro[$cp_num$]->MCR(ARMul_FIRST, $inst$, READ_REG($rd$));

	while (cpab == ARMul_BUSY) {
		if (emu->int_pending ()) {
			cpab = emu->copro[$cp_num$]->MCR(ARMul_INTERRUPT, $inst$, READ_REG($rd$));
		}
		else
			cpab = emu->copro[$cp_num$]->MCR(ARMul_BUSY, $inst$, READ_REG($rd$));
	}

	if (cpab == ARMul_CANT){
		ABORT2(UndefinedInstrV);
	}
"
}

op mrc(----1110:---1:----:rd:cp_num:---1:----){
execute="	
	if (emu->copro[$cp_num$] == NULL){
		ABORT2(UndefinedInstrV);
	}

	if (!CP_ACCESS_ALLOWED ($cp_num$)) {
		ABORT2(UndefinedInstrV);
	}
	
	cpab = emu->copro[$cp_num$]->MRC(ARMul_FIRST, $inst$, &val32);

	while (cpab == ARMul_BUSY) {
		if (emu->int_pending ()) {
			cpab = emu->copro[$cp_num$]->MRC(ARMul_INTERRUPT, $inst$, &val32);
		}
		else
			cpab = emu->copro[$cp_num$]->MRC(ARMul_BUSY, $inst$, &val32);
	}

	if (cpab == ARMul_CANT){
		ABORT2(UndefinedInstrV);
	}
	
	if ($rd$  == 15) {
		ASGN_N ((val32 & (1<<31)) != 0);
		ASGN_Z ((val32 & (1<<30)) != 0);