rtl_rtl8139_drv.h

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          0xf0fc0040, /* XXX copied from RTL8139B, verify */
        },
};


/* The rest of these values should never change. */
 
/* Symbolic offsets to registers. */
enum RTL8139_registers {
        MAC0 = 0,               /* Ethernet hardware address. */
        MAR0 = 8,               /* Multicast filter. */
        TxStatus0 = 0x10,       /* Transmit status (Four 32bit registers). */
        TxAddr0 = 0x20,         /* Tx descriptors (also four 32bit). */
        RxBuf = 0x30,
        RxEarlyCnt = 0x34,
        RxEarlyStatus = 0x36,
        ChipCmd = 0x37,
        RxBufPtr = 0x38,
        RxBufAddr = 0x3A,
        IntrMask = 0x3C,
        IntrStatus = 0x3E,
        TxConfig = 0x40,
        ChipVersion = 0x43,
        RxConfig = 0x44,
        Timer = 0x48,           /* A general-purpose counter. */
        RxMissed = 0x4C,        /* 24 bits valid, write clears. */
        Cfg9346 = 0x50,
        Config0 = 0x51,
        Config1 = 0x52,
        FlashReg = 0x54,
        MediaStatus = 0x58,
        Config3 = 0x59,
        Config4 = 0x5A,         /* absent on RTL-8139A */
        HltClk = 0x5B,
        MultiIntr = 0x5C,
        TxSummary = 0x60,
        BasicModeCtrl = 0x62,
        BasicModeStatus = 0x64,
        NWayAdvert = 0x66,
        NWayLPAR = 0x68,
        NWayExpansion = 0x6A,
        /* Undocumented registers, but required for proper operation. */
        FIFOTMS = 0x70,         /* FIFO Control and test. */
        CSCR = 0x74,            /* Chip Status and Configuration Register. */
        PARA78 = 0x78,
        PARA7c = 0x7c,          /* Magic transceiver parameter register. */
        Config5 = 0xD8,         /* absent on RTL-8139A */
//  For C+ Registers
        CPlusTxPoll=0xD9, CPlusCmd=0xE0, CPlusRxStartAddr=0xE4,
        CPlusTxStartAddr=0x20, CPlusEarlyTxThldReg=0xEC,
};


enum ClearBitMasks {
        MultiIntrClear = 0xF000,
        ChipCmdClear = 0xE2,
        Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
};
 
enum ChipCmdBits {
        CmdReset = 0x10,
        CmdRxEnb = 0x08,
        CmdTxEnb = 0x04,
        RxBufEmpty = 0x01,
};
 
enum CPlusCmdBits {
        CPlusTxEnb = 0x01,
        CPlusRxEnb = 0x02,
        CPlusCheckSumEnb = 0x20,
};

enum CPlusRxStatusDesc {
        CPlusRxRES = 0x00100000,
        CPlusRxCRC = 0x00040000,
        CPlusRxRUNT= 0x00080000,
        CPlusRxRWT = 0x00200000,
        CPlusRxFAE = 0x08000000,
        CPlusRxIPchecksumBIT  = 0x00008000,
        CPlusRxUDPIPchecksumBIT = 0x0000C000,
        CPlusRxTCPIPchecksumBIT = 0x0000A000,
        ProtocolType_NonIP        = 0,
        ProtocolType_TCPIP        = 1,
        ProtocolType_UDPIP        = 2,
        ProtocolType_IP           = 3,
};
 
enum CPlusTxChecksumOffload {
        CPlusTxIPchecksumOffload  = 0x00040000,
        CPlusTxUDPchecksumOffload = 0x00020000,
        CPlusTxTCPchecksumOffload = 0x00010000,
};

/* Interrupt register bits, using my own meaningful names. */
enum IntrStatusBits {
        PCIErr = 0x8000,
        PCSTimeout = 0x4000,
        RxFIFOOver = 0x40,
        RxUnderrun = 0x20,
        RxOverflow = 0x10,
        TxErr = 0x08,
        TxOK = 0x04,
        RxErr = 0x02,
        RxOK = 0x01,
};
enum TxStatusBits {
        TxHostOwns = 0x2000,
        TxUnderrun = 0x4000,
        TxStatOK = 0x8000,
        TxOutOfWindow = 0x20000000,
        TxAborted = 0x40000000,
        TxCarrierLost = 0x80000000,
};
enum RxStatusBits {
        RxMulticast = 0x8000,
        RxPhysical = 0x4000,
        RxBroadcast = 0x2000,
        RxBadSymbol = 0x0020,
        RxRunt = 0x0010,
        RxTooLong = 0x0008,
        RxCRCErr = 0x0004,
        RxBadAlign = 0x0002,
        RxStatusOK = 0x0001,
};

/* Bits in RxConfig. */
enum rx_mode_bits {
        AcceptErr = 0x20,
        AcceptRunt = 0x10,
        AcceptBroadcast = 0x08,
        AcceptMulticast = 0x04,
        AcceptMyPhys = 0x02,
        AcceptAllPhys = 0x01,
};
 
/* Bits in TxConfig. */
enum tx_config_bits {
        TxIFG1 = (1 << 25),     /* Interframe Gap Time */
        TxIFG0 = (1 << 24),     /* Enabling these bits violates IEEE 802.3 */
        TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
        TxCRC = (1 << 16),      /* DISABLE appending CRC to end of Tx packets */
        TxClearAbt = (1 << 0),  /* Clear abort (WO) */
        TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 
        TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
};

/* Bits in Config1 */
enum Config1Bits {
        Cfg1_PM_Enable = 0x01,
        Cfg1_VPD_Enable = 0x02,
        Cfg1_PIO = 0x04,
        Cfg1_MMIO = 0x08,
        Cfg1_LWAKE = 0x10,
        Cfg1_Driver_Load = 0x20,
        Cfg1_LED0 = 0x40,
        Cfg1_LED1 = 0x80,
};

enum RxConfigBits {
        /* Early Rx threshold, none or X/16 */
        RxCfgEarlyRxNone = 0,
        RxCfgEarlyRxShift = 24,
 
        /* rx fifo threshold */
        RxCfgFIFOShift = 13,
        RxCfgFIFONone = (7 << RxCfgFIFOShift),
 
        /* Max DMA burst */
        RxCfgDMAShift = 8,
        RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
 
        /* rx ring buffer length */
        RxCfgRcv8K = 0,
        RxCfgRcv16K = (1 << 11),
        RxCfgRcv32K = (1 << 12),
        RxCfgRcv64K = (1 << 11) | (1 << 12),
 
        /* Disable packet wrap at end of Rx buffer */
        RxNoWrap = (1 << 7),
};

/* Twister tuning parameters from RealTek.
   Completely undocumented, but required to tune bad links. */
enum CSCRBits {
        CSCR_LinkOKBit = 0x0400,
        CSCR_LinkChangeBit = 0x0800,
        CSCR_LinkStatusBits = 0x0f000,
        CSCR_LinkDownOffCmd = 0x003c0,
        CSCR_LinkDownCmd = 0x0f3c0,
};
 
 
enum Cfg9346Bits {
        Cfg9346_Lock = 0x00,
        Cfg9346_Unlock = 0xC0,
};
 
 
enum NegotiationBits {
        AutoNegotiationEnable  = 0x1000,
        AutoNegotiationRestart = 0x0200,
        AutoNegoAbility10half  = 0x21,
        AutoNegoAbility10full  = 0x41,
        AutoNegoAbility100half  = 0x81,
        AutoNegoAbility100full  = 0x101,
};
 
enum MediaStatusBits {
        DuplexMode = 0x0100,    //in BasicModeControlRegister
        Speed_10 = 0x08,                //in Media Status Register
};

/* A few user-configurable values. */
/* media options */
#define MAX_UNITS 8
static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
 
/* MII serial management: mostly bogus for now. */
/* Read and write the MII management registers using software-generated
   serial MDIO protocol.
   The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
   met by back-to-back PCI I/O cycles, but we insert a delay to avoid
   "overclocking" issues. */
#define MDIO_DIR                0x80
#define MDIO_DATA_OUT   0x04
#define MDIO_DATA_IN    0x02
#define MDIO_CLK                0x01
#define MDIO_WRITE0 (MDIO_DIR)
#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
 
#define rt_rtl8139_mdio_delay(mdio_addr)   readb(mdio_addr)
#define mdio_delay(mdio_addr)   readb(mdio_addr)
 
 
static char mii_2_8139_map[8] = {
        BasicModeCtrl,
        BasicModeStatus,
        0,
        0,
        NWayAdvert,
        NWayLPAR,
        NWayExpansion,
        0
};


 
/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
#define TX_BUF_SIZE     MAX_ETH_FRAME_SIZE
#define TX_BUF_TOT_LEN  (TX_BUF_SIZE * NUM_TX_DESC)
 
/* PCI Tuning Parameters
   Threshold is bytes transferred to chip before transmission starts. */
#define TX_FIFO_THRESH 256      /* In bytes, rounded down to 32 byte units. */

static const u16 rtl8139_intr_mask =
        PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
        TxErr | TxOK | RxErr | RxOK;
 
static const unsigned int rtl8139_rx_config =
          RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
          (RX_FIFO_THRESH << RxCfgFIFOShift) |
          (RX_DMA_BURST << RxCfgDMAShift);


/********************************************************************** */
 
struct rtl8139_private {
        void *mmio_addr;
        unsigned int mmio_len;
        int drv_flags;
        struct pci_dev *pci_dev;
        struct net_device_stats stats;
        unsigned char *rx_ring;
        unsigned int cur_rx;    /* Index into the Rx buffer of next Rx pkt. */
        unsigned int tx_flag;
        unsigned long cur_tx;
        unsigned long dirty_tx;
        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
        struct ring_info tx_info[NUM_TX_DESC];
        unsigned char *tx_buf[NUM_TX_DESC];     /* Tx bounce buffers */
        unsigned char *tx_bufs; /* Tx bounce buffer region. */
        dma_addr_t rx_ring_dma;
        dma_addr_t tx_bufs_dma;
        signed char phys[4];            /* MII device addresses. */
        u16 advertising;                /* NWay media advertisement */
        char twistie, twist_row, twist_col;     /* Twister tune state. */
        unsigned int full_duplex:1;     /* Full-duplex operation requested. */
        unsigned int duplex_lock:1;
        unsigned int default_port:4;    /* Last dev->if_port value. */
        unsigned int media2:4;  /* Secondary monitored media port. */
        unsigned int medialock:1;       /* Don't sense media type. */
        unsigned int mediasense:1;      /* Media sensing in progress. */
        spinlock_t lock;
        chip_t chipset;
        pid_t thr_pid;
        wait_queue_head_t thr_wait;
 
#if LINUX_VERSION_CODE < 0x20407
        struct semaphore thr_exited;
#else
        struct completion thr_exited;
#endif
 
 
  // For 8139C+
        int AutoNegoAbility;
        unsigned long CP_cur_tx;
        unsigned long CP_dirty_tx;
        unsigned long CP_cur_rx;
        unsigned char *TxDescArrays;
        unsigned char *RxDescArrays;
        struct CPlusTxDesc *TxDescArray;
        struct CPlusRxDesc *RxDescArray;
        unsigned char *RxBufferRings;
        unsigned char *RxBufferRing[NUM_CP_RX_DESC];
        struct sk_buff* Tx_skbuff[NUM_CP_TX_DESC];
/* For lwIP in RTLinux */
  int mtu;
  unsigned char dev_addr[MAX_ADDR_LEN]; /* hw address   */
  long ioaddr;
  unsigned long rx_packets;
  unsigned long rx_frames_for_us;
  unsigned char if_port;
  int must_free_irq;
  int must_free_region;
  unsigned char *rx_skbuff[RX_RING_SIZE];
  unsigned char *tx_skbuff[TX_RING_SIZE];


};


#define PCI_DEBUG 0
#define EEPROM_CONTENTS_DEBUG 0
#define MAC_ADDRESS_DEBUG 0
#define FUNCTION_CALL_DEBUG 0
#define INITIALIZATION_DEBUG 0
#define RECEIVE_DEBUG 0
#define PACKET_DATA_DEBUG 0
#define INTERRUPT_DEBUG 0
#define TRANSMIT_DEBUG 0
#define ERROR_DEBUG 1
 
#define SIGALRM2 RTL_SIGUSR1
 
#define DEBUG(x,y) if(x) printk y

#include <rtl_sync.h>
#include <rtl_core.h>
#include <rtl_printf.h>
#include <time.h>
#include <asm/io.h>
#include <rtl_posixio.h>
#include <sys/mman.h>
#include <errno.h>
#include <unistd.h>
#include <rtl.h>
#include <rtl_malloc.h>
#include <rtl_sema.h>
#include <rtl_sync.h>
#include "memcopy.h"

 
#define MAX_RX_BUFFER_ENTRIES 50

struct rx_buffer_t{
  struct rx_slot_t *first;
  struct rx_slot_t *add;
  struct rx_slot_t *extract;
}rx_buffer;



struct rx_slot_t{
  struct rx_slot_t *next;
  unsigned int length;
  unsigned char *data;
  unsigned char read;
#ifdef TIME_DEBUG
  struct timeval begin;
  struct timeval end;
#endif
};