rt_pci.h

最新rtlinux内核源码

/*********************************************************************************/
/* This file has been written by Sergio Perez Alca駃z <[e-mail]>    */
/*            Departamento de Inform醫ica de Sistemas y Computadores             */
/*            Universidad Polit閏nica de Valencia                                */
/*            Valencia (Spain)                                                   */
/*                                                                               */
/* The RTL-lwIP project has been supported by the Spanish Government Research    */
/* Office (CICYT) under grant TIC2002-04123-C03-03                               */
/*                                                                               */
/* Copyright (c) March, 2003 SISTEMAS DE TIEMPO REAL EMPOTRADOS, FIABLES Y       */
/* DISTRIBUIDOS BASADOS EN COMPONENTES                                           */
/*                                                                               */
/*  This program is free software; you can redistribute it and/or modify         */
/*  it under the terms of the GNU General Public License as published by         */
/*  the Free Software Foundation; either version 2 of the License, or            */
/*  (at your option) any later version.                                          */
/*                                                                               */
/*  This program is distributed in the hope that it will be useful,              */
/*  but WITHOUT ANY WARRANTY; without even the implied warranty of               */
/*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the                */
/*  GNU General Public License for more details.                                 */
/*                                                                               */
/*  You should have received a copy of the GNU General Public License            */
/*  along with this program; if not, write to the Free Software                  */
/*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA    */
/*                                                                               */
/*  Linking RTL-lwIP statically or dynamically with other modules is making a    */
/*  combined work based on RTL-lwIP.  Thus, the terms and conditions of the GNU  */
/*  General Public License cover the whole combination.                          */
/*                                                                               */
/*  As a special exception, the copyright holders of RTL-lwIP give you           */
/*  permission to link RTL-lwIP with independent modules that communicate with   */
/*  RTL-lwIP solely through the interfaces, regardless of the license terms of   */
/*  these independent modules, and to copy and distribute the resulting combined */
/*  work under terms of your choice, provided that every copy of the combined    */
/*  work is accompanied by a complete copy of the source code of RTL-lwIP (the   */
/*  version of RTL-lwIP used to produce the combined work), being distributed    */
/*  under the terms of the GNU General Public License plus this exception.  An   */
/*  independent module is a module which is not derived from or based on         */
/*  RTL-lwIP.                                                                    */
/*                                                                               */
/*  Note that people who make modified versions of RTL-lwIP are not obligated to */
/*  grant this special exception for their modified versions; it is their choice */
/*  whether to do so.  The GNU General Public License gives permission to        */
/*  release a modified version without this exception; this exception also makes */
/*  it possible to release a modified version which carries forward this         */
/*  exception.                                                                   */
/*                                                                               */
/*  CONTRIBUTORS: -Miguel Masmano Tello <[e-mail]>                  */
/*                -COMEDI                                                        */
/*                 The Linux Control and Measurement Device Interface            */
/*                 David Schleef <[e-mail]>                                */
/*********************************************************************************/

#include <linux/pci.h>
#include <linux/config.h>
#include <asm/io.h>
#ifndef	PCI_H
#define PCI_H

#define PCI_COMMAND_IO			0x1	/* Enable response in I/O space */
#define PCI_COMMAND_MEM			0x2	/* Enable response in mem space */
#define PCI_COMMAND_MASTER		0x4	/* Enable bus mastering */
#define PCI_LATENCY_TIMER		0x0d	/* 8 bits */

#define PCIBIOS_PCI_FUNCTION_ID         0xb1XX
#define PCIBIOS_PCI_BIOS_PRESENT        0xb101
#define PCIBIOS_FIND_PCI_DEVICE         0xb102
#define PCIBIOS_FIND_PCI_CLASS_CODE     0xb103
#define PCIBIOS_GENERATE_SPECIAL_CYCLE  0xb106
#define PCIBIOS_READ_CONFIG_BYTE        0xb108
#define PCIBIOS_READ_CONFIG_WORD        0xb109
#define PCIBIOS_READ_CONFIG_DWORD       0xb10a
#define PCIBIOS_WRITE_CONFIG_BYTE       0xb10b
#define PCIBIOS_WRITE_CONFIG_WORD       0xb10c
#define PCIBIOS_WRITE_CONFIG_DWORD      0xb10d
#define PCIBIOS_SET_PCI_HW_INT          0xb10f

#define PCI_VENDOR_ID           0x00    /* 16 bits */
#define PCI_DEVICE_ID           0x02    /* 16 bits */
#define PCI_COMMAND             0x04    /* 16 bits */

#define PCI_REVISION            0x08    /* 8 bits  */
#define PCI_CLASS_CODE          0x0b    /* 8 bits */
#define PCI_SUBCLASS_CODE       0x0a    /* 8 bits */
#define PCI_HEADER_TYPE         0x0e    /* 8 bits */

#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits */
#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits */
#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */

#define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
#define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */

#ifndef	PCI_BASE_ADDRESS_IO_MASK
#define	PCI_BASE_ADDRESS_IO_MASK       (~0x03)
#endif
#define	PCI_BASE_ADDRESS_SPACE_IO	0x01
#define	PCI_ROM_ADDRESS		0x30	/* 32 bits */
#define	PCI_ROM_ADDRESS_ENABLE	0x01	/* Write 1 to enable ROM,
					   bits 31..11 are address,
					   10..2 are reserved */

#define PCI_FUNC(devfn)           ((devfn) & 0x07)

#define bus_number(pci_dev) ((((int)(pci_dev))>>8) & 0xff)
#define devfn_number(pci_dev) (((int)(pci_dev)) & 0xff)


#define BIOS32_SIGNATURE        (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))

/* PCI signature: "PCI " */
#define PCI_SIGNATURE           (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))

/* PCI service signature: "$PCI" */
#define PCI_SERVICE             (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))

union bios32 {
  struct {
    unsigned long signature;	/* _32_ */
    unsigned long entry;	/* Direccion fisica de 32 bit */
    unsigned char revision;		/* Nivel de revision */
    unsigned char length;		/* La longitud deberia ser 01 */
    unsigned char checksum;		/* Todos los bytes deberian ser cero */
    unsigned char reserved[5];	/* Debe ser cero */
  } fields;
  char chars[16];
};

#define KERN_CODE_SEG	0x10	/* Esto coincide con oskit/base_gdt.h KERNEL_CS */


extern int rt_pcibios_read_config_byte(unsigned int bus, unsigned int device_fn, 
				    unsigned int where, unsigned char *value);

extern int rt_rtpcibios_write_config_byte (unsigned int bus, unsigned int device_fn,
				      unsigned int where, unsigned char value);

extern int rt_pcibios_read_config_word(unsigned int bus, unsigned int device_fn, 
				    unsigned int where, unsigned short *value);

extern int rt_pcibios_write_config_word (unsigned int bus, unsigned int device_fn,
				      unsigned int where, unsigned short value);

extern int rt_pcibios_read_config_dword(unsigned int bus, unsigned int device_fn, 
				     unsigned int where, unsigned int *value);

extern int rt_pcibios_write_config_dword(unsigned int bus, unsigned int device_fn,
				      unsigned int where, unsigned int value);

extern int rt_pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);

#define rt_pci_read_config_byte(pdev, where, valp)\
	rt_pcibios_read_config_byte(bus_number(pdev), devfn_number(pdev), where, valp)
#define rt_pci_read_config_word(pdev, where, valp)\
	rt_pcibios_read_config_word(bus_number(pdev), devfn_number(pdev), where, valp)
#define rt_pci_read_config_dword(pdev, where, valp)\
	rt_pcibios_read_config_dword(bus_number(pdev), devfn_number(pdev), where, valp)
#define rt_pci_write_config_byte(pdev, where, val)\
	rt_pcibios_write_config_byte(bus_number(pdev), devfn_number(pdev), where, val)
#define rt_pci_write_config_word(pdev, where, val)\
	rt_pcibios_write_config_word(bus_number(pdev), devfn_number(pdev), where, val)
#define rt_pci_write_config_dword(pdev, where, val)\
	rt_pcibios_write_config_dword(bus_number(pdev), devfn_number(pdev), where, val)

#define rt_pci_resource_start(dev,bar)   ((dev)->resource[(bar)].start)
#define rt_pci_resource_end(dev,bar)     ((dev)->resource[(bar)].end)
#define rt_pci_resource_flags(dev,bar)   ((dev)->resource[(bar)].flags)
#define rt_pci_resource_len(dev,bar) \
	((rt_pci_resource_start((dev),(bar)) == 0 &&	\
	  rt_pci_resource_end((dev),(bar)) ==		\
	  rt_pci_resource_start((dev),(bar))) ? 0 :	\
	  						\
	 (rt_pci_resource_end((dev),(bar)) -		\
	  rt_pci_resource_start((dev),(bar)) + 1))




int rt_pci_set_power_state(struct pci_dev *dev, int state);
int rt_pci_find_capability(struct pci_dev *dev, int cap);
struct pci_dev * rt_pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from);
int rt_pci_enable_device(struct pci_dev *dev);
int rt_pci_restore_state(struct pci_dev *dev, u32 *buffer);
int rt_pci_enable_wake(struct pci_dev *dev, u32 state, int enable);
int rt_pci_save_state(struct pci_dev *dev, u32 *buffer);
#endif	/* PCI_H */