prev_cmp_temp.map.qmsg

完整的4*4键盘程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 28 09:35:27 2008 " "Info: Processing started: Fri Nov 28 09:35:27 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off temp -c temp " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off temp -c temp" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../ff/yanshi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../ff/yanshi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 yanshi-debounce_architecture " "Info: Found design unit 1: yanshi-debounce_architecture" {  } { { "../ff/yanshi.vhd" "" { Text "F:/alter/2sfenpin/jianpan/ff/yanshi.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 yanshi " "Info: Found entity 1: yanshi" {  } { { "../ff/yanshi.vhd" "" { Text "F:/alter/2sfenpin/jianpan/ff/yanshi.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "temp.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file temp.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 temp-art " "Info: Found design unit 1: temp-art" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 temp " "Info: Found entity 1: temp" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "temp " "Info: Elaborating entity \"temp\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "inkeymap temp.vhd(25) " "Warning (10036): Verilog HDL or VHDL warning at temp.vhd(25): object \"inkeymap\" assigned a value but never read" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 25 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "yanshi yanshi:\\roll:0:movskipx " "Info: Elaborating entity \"yanshi\" for hierarchy \"yanshi:\\roll:0:movskipx\"" {  } { { "temp.vhd" "\\roll:0:movskipx" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 30 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "p GND " "Warning (13410): Pin \"p\" stuck at GND" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "100 " "Info: Implemented 100 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "82 " "Info: Implemented 82 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 28 09:35:33 2008 " "Info: Processing ended: Fri Nov 28 09:35:33 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}