temp.tan.qmsg

完整的4*4键盘程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "keyclkout " "Info: Detected ripple clock \"keyclkout\" as buffer" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "keyclkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "chuclkout " "Info: Detected ripple clock \"chuclkout\" as buffer" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "chuclkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "inclk register keyclk\[7\] register keyclk\[17\] 212.86 MHz 4.698 ns Internal " "Info: Clock \"inclk\" has Internal fmax of 212.86 MHz between source register \"keyclk\[7\]\" and destination register \"keyclk\[17\]\" (period= 4.698 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.434 ns + Longest register register " "Info: + Longest register to register delay is 4.434 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyclk\[7\] 1 REG LCFF_X1_Y8_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y8_N29; Fanout = 3; REG Node = 'keyclk\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyclk[7] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.416 ns) + CELL(0.206 ns) 1.622 ns Equal0~172 2 COMB LCCOMB_X1_Y9_N6 1 " "Info: 2: + IC(1.416 ns) + CELL(0.206 ns) = 1.622 ns; Loc. = LCCOMB_X1_Y9_N6; Fanout = 1; COMB Node = 'Equal0~172'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.622 ns" { keyclk[7] Equal0~172 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.614 ns) 2.632 ns Equal0~175 3 COMB LCCOMB_X1_Y9_N10 9 " "Info: 3: + IC(0.396 ns) + CELL(0.614 ns) = 2.632 ns; Loc. = LCCOMB_X1_Y9_N10; Fanout = 9; COMB Node = 'Equal0~175'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.010 ns" { Equal0~172 Equal0~175 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(0.580 ns) 4.326 ns keyclk~531 4 COMB LCCOMB_X1_Y8_N26 1 " "Info: 4: + IC(1.114 ns) + CELL(0.580 ns) = 4.326 ns; Loc. = LCCOMB_X1_Y8_N26; Fanout = 1; COMB Node = 'keyclk~531'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.694 ns" { Equal0~175 keyclk~531 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.434 ns keyclk\[17\] 5 REG LCFF_X1_Y8_N27 10 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 4.434 ns; Loc. = LCFF_X1_Y8_N27; Fanout = 10; REG Node = 'keyclk\[17\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { keyclk~531 keyclk[17] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.508 ns ( 34.01 % ) " "Info: Total cell delay = 1.508 ns ( 34.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.926 ns ( 65.99 % ) " "Info: Total interconnect delay = 2.926 ns ( 65.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.434 ns" { keyclk[7] Equal0~172 Equal0~175 keyclk~531 keyclk[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.434 ns" { keyclk[7] {} Equal0~172 {} Equal0~175 {} keyclk~531 {} keyclk[17] {} } { 0.000ns 1.416ns 0.396ns 1.114ns 0.000ns } { 0.000ns 0.206ns 0.614ns 0.580ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 2.785 ns + Shortest register " "Info: + Shortest clock path from clock \"inclk\" to destination register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inclk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'inclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns inclk~clkctrl 2 COMB CLKCTRL_G2 18 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'inclk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { inclk inclk~clkctrl } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.785 ns keyclk\[17\] 3 REG LCFF_X1_Y8_N27 10 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N27; Fanout = 10; REG Node = 'keyclk\[17\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { inclk~clkctrl keyclk[17] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.05 % ) " "Info: Total cell delay = 1.756 ns ( 63.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.95 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { inclk inclk~clkctrl keyclk[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[17] {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 2.785 ns - Longest register " "Info: - Longest clock path from clock \"inclk\" to source register is 2.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inclk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'inclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns inclk~clkctrl 2 COMB CLKCTRL_G2 18 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'inclk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { inclk inclk~clkctrl } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.785 ns keyclk\[7\] 3 REG LCFF_X1_Y8_N29 3 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.785 ns; Loc. = LCFF_X1_Y8_N29; Fanout = 3; REG Node = 'keyclk\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { inclk~clkctrl keyclk[7] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.05 % ) " "Info: Total cell delay = 1.756 ns ( 63.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.95 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { inclk inclk~clkctrl keyclk[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[7] {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { inclk inclk~clkctrl keyclk[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[17] {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { inclk inclk~clkctrl keyclk[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[7] {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.434 ns" { keyclk[7] Equal0~172 Equal0~175 keyclk~531 keyclk[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.434 ns" { keyclk[7] {} Equal0~172 {} Equal0~175 {} keyclk~531 {} keyclk[17] {} } { 0.000ns 1.416ns 0.396ns 1.114ns 0.000ns } { 0.000ns 0.206ns 0.614ns 0.580ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { inclk inclk~clkctrl keyclk[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[17] {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.785 ns" { inclk inclk~clkctrl keyclk[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.785 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[7] {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "outled\[0\]~reg0 inkey\[2\] inclk 3.477 ns register " "Info: tsu for register \"outled\[0\]~reg0\" (data pin = \"inkey\[2\]\", clock pin = \"inclk\") is 3.477 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.205 ns + Longest pin register " "Info: + Longest pin to register delay is 11.205 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns inkey\[2\] 1 PIN PIN_119 12 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_119; Fanout = 12; PIN Node = 'inkey\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inkey[2] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.871 ns) + CELL(0.577 ns) 8.382 ns outled\[0\]~7770 2 COMB LCCOMB_X26_Y10_N10 1 " "Info: 2: + IC(6.871 ns) + CELL(0.577 ns) = 8.382 ns; Loc. = LCCOMB_X26_Y10_N10; Fanout = 1; COMB Node = 'outled\[0\]~7770'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.448 ns" { inkey[2] outled[0]~7770 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.062 ns) + CELL(0.651 ns) 10.095 ns outled\[0\]~7743 3 COMB LCCOMB_X24_Y10_N22 1 " "Info: 3: + IC(1.062 ns) + CELL(0.651 ns) = 10.095 ns; Loc. = LCCOMB_X24_Y10_N22; Fanout = 1; COMB Node = 'outled\[0\]~7743'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.713 ns" { outled[0]~7770 outled[0]~7743 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.624 ns) 11.097 ns outled\[0\]~7744 4 COMB LCCOMB_X24_Y10_N8 1 " "Info: 4: + IC(0.378 ns) + CELL(0.624 ns) = 11.097 ns; Loc. = LCCOMB_X24_Y10_N8; Fanout = 1; COMB Node = 'outled\[0\]~7744'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.002 ns" { outled[0]~7743 outled[0]~7744 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 11.205 ns outled\[0\]~reg0 5 REG LCFF_X24_Y10_N9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 11.205 ns; Loc. = LCFF_X24_Y10_N9; Fanout = 2; REG Node = 'outled\[0\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { outled[0]~7744 outled[0]~reg0 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.894 ns ( 25.83 % ) " "Info: Total cell delay = 2.894 ns ( 25.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.311 ns ( 74.17 % ) " "Info: Total interconnect delay = 8.311 ns ( 74.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.205 ns" { inkey[2] outled[0]~7770 outled[0]~7743 outled[0]~7744 outled[0]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.205 ns" { inkey[2] {} inkey[2]~combout {} outled[0]~7770 {} outled[0]~7743 {} outled[0]~7744 {} outled[0]~reg0 {} } { 0.000ns 0.000ns 6.871ns 1.062ns 0.378ns 0.000ns } { 0.000ns 0.934ns 0.577ns 0.651ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 7.688 ns - Shortest register " "Info: - Shortest clock path from clock \"inclk\" to destination register is 7.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inclk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'inclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.970 ns) 2.986 ns keyclkout 2 REG LCFF_X1_Y8_N25 3 " "Info: 2: + IC(0.926 ns) + CELL(0.970 ns) = 2.986 ns; Loc. = LCFF_X1_Y8_N25; Fanout = 3; REG Node = 'keyclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.896 ns" { inclk keyclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.970 ns) 5.023 ns chuclkout 3 REG LCFF_X2_Y9_N21 2 " "Info: 3: + IC(1.067 ns) + CELL(0.970 ns) = 5.023 ns; Loc. = LCFF_X2_Y9_N21; Fanout = 2; REG Node = 'chuclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.037 ns" { keyclkout chuclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.000 ns) 6.152 ns chuclkout~clkctrl 4 COMB CLKCTRL_G3 13 " "Info: 4: + IC(1.129 ns) + CELL(0.000 ns) = 6.152 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'chuclkout~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.129 ns" { chuclkout chuclkout~clkctrl } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.870 ns) + CELL(0.666 ns) 7.688 ns outled\[0\]~reg0 5 REG LCFF_X24_Y10_N9 2 " "Info: 5: + IC(0.870 ns) + CELL(0.666 ns) = 7.688 ns; Loc. = LCFF_X24_Y10_N9; Fanout = 2; REG Node = 'outled\[0\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { chuclkout~clkctrl outled[0]~reg0 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 48.07 % ) " "Info: Total cell delay = 3.696 ns ( 48.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.992 ns ( 51.93 % ) " "Info: Total interconnect delay = 3.992 ns ( 51.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.688 ns" { inclk keyclkout chuclkout chuclkout~clkctrl outled[0]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.688 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} outled[0]~reg0 {} } { 0.000ns 0.000ns 0.926ns 1.067ns 1.129ns 0.870ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.205 ns" { inkey[2] outled[0]~7770 outled[0]~7743 outled[0]~7744 outled[0]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.205 ns" { inkey[2] {} inkey[2]~combout {} outled[0]~7770 {} outled[0]~7743 {} outled[0]~7744 {} outled[0]~reg0 {} } { 0.000ns 0.000ns 6.871ns 1.062ns 0.378ns 0.000ns } { 0.000ns 0.934ns 0.577ns 0.651ns 0.624ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.688 ns" { inclk keyclkout chuclkout chuclkout~clkctrl outled[0]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.688 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} outled[0]~reg0 {} } { 0.000ns 0.000ns 0.926ns 1.067ns 1.129ns 0.870ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclk outkey\[0\] chuout\[0\] 14.908 ns register " "Info: tco from clock \"inclk\" to destination pin \"outkey\[0\]\" through register \"chuout\[0\]\" is 14.908 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 7.689 ns + Longest register " "Info: + Longest clock path from clock \"inclk\" to source register is 7.689 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inclk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'inclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.970 ns) 2.986 ns keyclkout 2 REG LCFF_X1_Y8_N25 3 " "Info: 2: + IC(0.926 ns) + CELL(0.970 ns) = 2.986 ns; Loc. = LCFF_X1_Y8_N25; Fanout = 3; REG Node = 'keyclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.896 ns" { inclk keyclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.970 ns) 5.023 ns chuclkout 3 REG LCFF_X2_Y9_N21 2 " "Info: 3: + IC(1.067 ns) + CELL(0.970 ns) = 5.023 ns; Loc. = LCFF_X2_Y9_N21; Fanout = 2; REG Node = 'chuclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.037 ns" { keyclkout chuclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.000 ns) 6.152 ns chuclkout~clkctrl 4 COMB CLKCTRL_G3 13 " "Info: 4: + IC(1.129 ns) + CELL(0.000 ns) = 6.152 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'chuclkout~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.129 ns" { chuclkout chuclkout~clkctrl } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 7.689 ns chuout\[0\] 5 REG LCFF_X25_Y10_N31 17 " "Info: 5: + IC(0.871 ns) + CELL(0.666 ns) = 7.689 ns; Loc. = LCFF_X25_Y10_N31; Fanout = 17; REG Node = 'chuout\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { chuclkout~clkctrl chuout[0] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 48.07 % ) " "Info: Total cell delay = 3.696 ns ( 48.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.993 ns ( 51.93 % ) " "Info: Total interconnect delay = 3.993 ns ( 51.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.689 ns" { inclk keyclkout chuclkout chuclkout~clkctrl chuout[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.689 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} chuout[0] {} } { 0.000ns 0.000ns 0.926ns 1.067ns 1.129ns 0.871ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.915 ns + Longest register pin " "Info: + Longest register to pin delay is 6.915 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns chuout\[0\] 1 REG LCFF_X25_Y10_N31 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y10_N31; Fanout = 17; REG Node = 'chuout\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { chuout[0] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.679 ns) + CELL(3.236 ns) 6.915 ns outkey\[0\] 2 PIN PIN_135 0 " "Info: 2: + IC(3.679 ns) + CELL(3.236 ns) = 6.915 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'outkey\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.915 ns" { chuout[0] outkey[0] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 46.80 % ) " "Info: Total cell delay = 3.236 ns ( 46.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.679 ns ( 53.20 % ) " "Info: Total interconnect delay = 3.679 ns ( 53.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.915 ns" { chuout[0] outkey[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.915 ns" { chuout[0] {} outkey[0] {} } { 0.000ns 3.679ns } { 0.000ns 3.236ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.689 ns" { inclk keyclkout chuclkout chuclkout~clkctrl chuout[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.689 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} chuout[0] {} } { 0.000ns 0.000ns 0.926ns 1.067ns 1.129ns 0.871ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.915 ns" { chuout[0] outkey[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.915 ns" { chuout[0] {} outkey[0] {} } { 0.000ns 3.679ns } { 0.000ns 3.236ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}