prev_cmp_temp.tan.qmsg

完整的4*4键盘程序

{ "Info" "ITDB_TH_RESULT" "chuout\[2\] reset inclk 1.062 ns register " "Info: th for register \"chuout\[2\]\" (data pin = \"reset\", clock pin = \"inclk\") is 1.062 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 9.219 ns + Longest register " "Info: + Longest clock path from clock \"inclk\" to destination register is 9.219 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inclk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'inclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.975 ns) + CELL(0.970 ns) 3.035 ns keyclkout 2 REG LCFF_X1_Y7_N31 3 " "Info: 2: + IC(0.975 ns) + CELL(0.970 ns) = 3.035 ns; Loc. = LCFF_X1_Y7_N31; Fanout = 3; REG Node = 'keyclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.945 ns" { inclk keyclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.203 ns) + CELL(0.970 ns) 6.208 ns chuclkout 3 REG LCFF_X28_Y11_N17 2 " "Info: 3: + IC(2.203 ns) + CELL(0.970 ns) = 6.208 ns; Loc. = LCFF_X28_Y11_N17; Fanout = 2; REG Node = 'chuclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.173 ns" { keyclkout chuclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.000 ns) 7.631 ns chuclkout~clkctrl 4 COMB CLKCTRL_G7 13 " "Info: 4: + IC(1.423 ns) + CELL(0.000 ns) = 7.631 ns; Loc. = CLKCTRL_G7; Fanout = 13; COMB Node = 'chuclkout~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.423 ns" { chuclkout chuclkout~clkctrl } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.666 ns) 9.219 ns chuout\[2\] 5 REG LCFF_X10_Y15_N11 15 " "Info: 5: + IC(0.922 ns) + CELL(0.666 ns) = 9.219 ns; Loc. = LCFF_X10_Y15_N11; Fanout = 15; REG Node = 'chuout\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.588 ns" { chuclkout~clkctrl chuout[2] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 40.09 % ) " "Info: Total cell delay = 3.696 ns ( 40.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.523 ns ( 59.91 % ) " "Info: Total interconnect delay = 5.523 ns ( 59.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.219 ns" { inclk keyclkout chuclkout chuclkout~clkctrl chuout[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.219 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} chuout[2] {} } { 0.000ns 0.000ns 0.975ns 2.203ns 1.423ns 0.922ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.463 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns reset 1 PIN PIN_24 5 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_24; Fanout = 5; PIN Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.663 ns) + CELL(0.855 ns) 8.463 ns chuout\[2\] 2 REG LCFF_X10_Y15_N11 15 " "Info: 2: + IC(6.663 ns) + CELL(0.855 ns) = 8.463 ns; Loc. = LCFF_X10_Y15_N11; Fanout = 15; REG Node = 'chuout\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.518 ns" { reset chuout[2] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns ( 21.27 % ) " "Info: Total cell delay = 1.800 ns ( 21.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.663 ns ( 78.73 % ) " "Info: Total interconnect delay = 6.663 ns ( 78.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.463 ns" { reset chuout[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.463 ns" { reset {} reset~combout {} chuout[2] {} } { 0.000ns 0.000ns 6.663ns } { 0.000ns 0.945ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.219 ns" { inclk keyclkout chuclkout chuclkout~clkctrl chuout[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.219 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} chuout[2] {} } { 0.000ns 0.000ns 0.975ns 2.203ns 1.423ns 0.922ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.463 ns" { reset chuout[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.463 ns" { reset {} reset~combout {} chuout[2] {} } { 0.000ns 0.000ns 6.663ns } { 0.000ns 0.945ns 0.855ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 28 09:35:53 2008 " "Info: Processing ended: Fri Nov 28 09:35:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}