prev_cmp_temp.tan.qmsg

完整的4*4键盘程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "keyclkout " "Info: Detected ripple clock \"keyclkout\" as buffer" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "keyclkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "chuclkout " "Info: Detected ripple clock \"chuclkout\" as buffer" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "chuclkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "inclk register keyclk\[7\] register keyclk\[16\] 216.68 MHz 4.615 ns Internal " "Info: Clock \"inclk\" has Internal fmax of 216.68 MHz between source register \"keyclk\[7\]\" and destination register \"keyclk\[16\]\" (period= 4.615 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.351 ns + Longest register register " "Info: + Longest register to register delay is 4.351 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyclk\[7\] 1 REG LCFF_X1_Y7_N21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y7_N21; Fanout = 3; REG Node = 'keyclk\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyclk[7] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.142 ns) + CELL(0.370 ns) 1.512 ns Equal0~172 2 COMB LCCOMB_X1_Y8_N6 1 " "Info: 2: + IC(1.142 ns) + CELL(0.370 ns) = 1.512 ns; Loc. = LCCOMB_X1_Y8_N6; Fanout = 1; COMB Node = 'Equal0~172'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.512 ns" { keyclk[7] Equal0~172 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.614 ns) 2.523 ns Equal0~175 3 COMB LCCOMB_X1_Y8_N12 9 " "Info: 3: + IC(0.397 ns) + CELL(0.614 ns) = 2.523 ns; Loc. = LCCOMB_X1_Y8_N12; Fanout = 9; COMB Node = 'Equal0~175'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.011 ns" { Equal0~172 Equal0~175 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.105 ns) + CELL(0.615 ns) 4.243 ns keyclk~530 4 COMB LCCOMB_X1_Y7_N18 1 " "Info: 4: + IC(1.105 ns) + CELL(0.615 ns) = 4.243 ns; Loc. = LCCOMB_X1_Y7_N18; Fanout = 1; COMB Node = 'keyclk~530'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { Equal0~175 keyclk~530 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.351 ns keyclk\[16\] 5 REG LCFF_X1_Y7_N19 11 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 4.351 ns; Loc. = LCFF_X1_Y7_N19; Fanout = 11; REG Node = 'keyclk\[16\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { keyclk~530 keyclk[16] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.707 ns ( 39.23 % ) " "Info: Total cell delay = 1.707 ns ( 39.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.644 ns ( 60.77 % ) " "Info: Total interconnect delay = 2.644 ns ( 60.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.351 ns" { keyclk[7] Equal0~172 Equal0~175 keyclk~530 keyclk[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.351 ns" { keyclk[7] {} Equal0~172 {} Equal0~175 {} keyclk~530 {} keyclk[16] {} } { 0.000ns 1.142ns 0.397ns 1.105ns 0.000ns } { 0.000ns 0.370ns 0.614ns 0.615ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 2.794 ns + Shortest register " "Info: + Shortest clock path from clock \"inclk\" to destination register is 2.794 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inclk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'inclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns inclk~clkctrl 2 COMB CLKCTRL_G2 18 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'inclk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { inclk inclk~clkctrl } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.666 ns) 2.794 ns keyclk\[16\] 3 REG LCFF_X1_Y7_N19 11 " "Info: 3: + IC(0.899 ns) + CELL(0.666 ns) = 2.794 ns; Loc. = LCFF_X1_Y7_N19; Fanout = 11; REG Node = 'keyclk\[16\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { inclk~clkctrl keyclk[16] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.85 % ) " "Info: Total cell delay = 1.756 ns ( 62.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.038 ns ( 37.15 % ) " "Info: Total interconnect delay = 1.038 ns ( 37.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { inclk inclk~clkctrl keyclk[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[16] {} } { 0.000ns 0.000ns 0.139ns 0.899ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 2.794 ns - Longest register " "Info: - Longest clock path from clock \"inclk\" to source register is 2.794 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inclk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'inclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns inclk~clkctrl 2 COMB CLKCTRL_G2 18 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'inclk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { inclk inclk~clkctrl } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.666 ns) 2.794 ns keyclk\[7\] 3 REG LCFF_X1_Y7_N21 3 " "Info: 3: + IC(0.899 ns) + CELL(0.666 ns) = 2.794 ns; Loc. = LCFF_X1_Y7_N21; Fanout = 3; REG Node = 'keyclk\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { inclk~clkctrl keyclk[7] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.85 % ) " "Info: Total cell delay = 1.756 ns ( 62.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.038 ns ( 37.15 % ) " "Info: Total interconnect delay = 1.038 ns ( 37.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { inclk inclk~clkctrl keyclk[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[7] {} } { 0.000ns 0.000ns 0.139ns 0.899ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { inclk inclk~clkctrl keyclk[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[16] {} } { 0.000ns 0.000ns 0.139ns 0.899ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { inclk inclk~clkctrl keyclk[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[7] {} } { 0.000ns 0.000ns 0.139ns 0.899ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.351 ns" { keyclk[7] Equal0~172 Equal0~175 keyclk~530 keyclk[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.351 ns" { keyclk[7] {} Equal0~172 {} Equal0~175 {} keyclk~530 {} keyclk[16] {} } { 0.000ns 1.142ns 0.397ns 1.105ns 0.000ns } { 0.000ns 0.370ns 0.614ns 0.615ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { inclk inclk~clkctrl keyclk[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[16] {} } { 0.000ns 0.000ns 0.139ns 0.899ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.794 ns" { inclk inclk~clkctrl keyclk[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.794 ns" { inclk {} inclk~combout {} inclk~clkctrl {} keyclk[7] {} } { 0.000ns 0.000ns 0.139ns 0.899ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "outled\[5\]~reg0 inkey\[1\] inclk 2.611 ns register " "Info: tsu for register \"outled\[5\]~reg0\" (data pin = \"inkey\[1\]\", clock pin = \"inclk\") is 2.611 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.884 ns + Longest pin register " "Info: + Longest pin to register delay is 11.884 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns inkey\[1\] 1 PIN PIN_115 7 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_115; Fanout = 7; PIN Node = 'inkey\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inkey[1] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.878 ns) + CELL(0.624 ns) 8.436 ns outled\[0\]~7172 2 COMB LCCOMB_X17_Y15_N26 2 " "Info: 2: + IC(6.878 ns) + CELL(0.624 ns) = 8.436 ns; Loc. = LCCOMB_X17_Y15_N26; Fanout = 2; COMB Node = 'outled\[0\]~7172'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.502 ns" { inkey[1] outled[0]~7172 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.124 ns) + CELL(0.650 ns) 11.210 ns outled\[0\]~7188 3 COMB LCCOMB_X16_Y17_N10 1 " "Info: 3: + IC(2.124 ns) + CELL(0.650 ns) = 11.210 ns; Loc. = LCCOMB_X16_Y17_N10; Fanout = 1; COMB Node = 'outled\[0\]~7188'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { outled[0]~7172 outled[0]~7188 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.206 ns) 11.776 ns outled\[5\]~3457 4 COMB LCCOMB_X16_Y17_N26 1 " "Info: 4: + IC(0.360 ns) + CELL(0.206 ns) = 11.776 ns; Loc. = LCCOMB_X16_Y17_N26; Fanout = 1; COMB Node = 'outled\[5\]~3457'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.566 ns" { outled[0]~7188 outled[5]~3457 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 11.884 ns outled\[5\]~reg0 5 REG LCFF_X16_Y17_N27 4 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 11.884 ns; Loc. = LCFF_X16_Y17_N27; Fanout = 4; REG Node = 'outled\[5\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { outled[5]~3457 outled[5]~reg0 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.522 ns ( 21.22 % ) " "Info: Total cell delay = 2.522 ns ( 21.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.362 ns ( 78.78 % ) " "Info: Total interconnect delay = 9.362 ns ( 78.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.884 ns" { inkey[1] outled[0]~7172 outled[0]~7188 outled[5]~3457 outled[5]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.884 ns" { inkey[1] {} inkey[1]~combout {} outled[0]~7172 {} outled[0]~7188 {} outled[5]~3457 {} outled[5]~reg0 {} } { 0.000ns 0.000ns 6.878ns 2.124ns 0.360ns 0.000ns } { 0.000ns 0.934ns 0.624ns 0.650ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 9.233 ns - Shortest register " "Info: - Shortest clock path from clock \"inclk\" to destination register is 9.233 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inclk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'inclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.975 ns) + CELL(0.970 ns) 3.035 ns keyclkout 2 REG LCFF_X1_Y7_N31 3 " "Info: 2: + IC(0.975 ns) + CELL(0.970 ns) = 3.035 ns; Loc. = LCFF_X1_Y7_N31; Fanout = 3; REG Node = 'keyclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.945 ns" { inclk keyclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.203 ns) + CELL(0.970 ns) 6.208 ns chuclkout 3 REG LCFF_X28_Y11_N17 2 " "Info: 3: + IC(2.203 ns) + CELL(0.970 ns) = 6.208 ns; Loc. = LCFF_X28_Y11_N17; Fanout = 2; REG Node = 'chuclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.173 ns" { keyclkout chuclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.000 ns) 7.631 ns chuclkout~clkctrl 4 COMB CLKCTRL_G7 13 " "Info: 4: + IC(1.423 ns) + CELL(0.000 ns) = 7.631 ns; Loc. = CLKCTRL_G7; Fanout = 13; COMB Node = 'chuclkout~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.423 ns" { chuclkout chuclkout~clkctrl } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.936 ns) + CELL(0.666 ns) 9.233 ns outled\[5\]~reg0 5 REG LCFF_X16_Y17_N27 4 " "Info: 5: + IC(0.936 ns) + CELL(0.666 ns) = 9.233 ns; Loc. = LCFF_X16_Y17_N27; Fanout = 4; REG Node = 'outled\[5\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.602 ns" { chuclkout~clkctrl outled[5]~reg0 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 40.03 % ) " "Info: Total cell delay = 3.696 ns ( 40.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.537 ns ( 59.97 % ) " "Info: Total interconnect delay = 5.537 ns ( 59.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.233 ns" { inclk keyclkout chuclkout chuclkout~clkctrl outled[5]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.233 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} outled[5]~reg0 {} } { 0.000ns 0.000ns 0.975ns 2.203ns 1.423ns 0.936ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.884 ns" { inkey[1] outled[0]~7172 outled[0]~7188 outled[5]~3457 outled[5]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.884 ns" { inkey[1] {} inkey[1]~combout {} outled[0]~7172 {} outled[0]~7188 {} outled[5]~3457 {} outled[5]~reg0 {} } { 0.000ns 0.000ns 6.878ns 2.124ns 0.360ns 0.000ns } { 0.000ns 0.934ns 0.624ns 0.650ns 0.206ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.233 ns" { inclk keyclkout chuclkout chuclkout~clkctrl outled[5]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.233 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} outled[5]~reg0 {} } { 0.000ns 0.000ns 0.975ns 2.203ns 1.423ns 0.936ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclk outled\[1\] outled\[1\]~reg0 16.558 ns register " "Info: tco from clock \"inclk\" to destination pin \"outled\[1\]\" through register \"outled\[1\]~reg0\" is 16.558 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 9.229 ns + Longest register " "Info: + Longest clock path from clock \"inclk\" to source register is 9.229 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns inclk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'inclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.975 ns) + CELL(0.970 ns) 3.035 ns keyclkout 2 REG LCFF_X1_Y7_N31 3 " "Info: 2: + IC(0.975 ns) + CELL(0.970 ns) = 3.035 ns; Loc. = LCFF_X1_Y7_N31; Fanout = 3; REG Node = 'keyclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.945 ns" { inclk keyclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.203 ns) + CELL(0.970 ns) 6.208 ns chuclkout 3 REG LCFF_X28_Y11_N17 2 " "Info: 3: + IC(2.203 ns) + CELL(0.970 ns) = 6.208 ns; Loc. = LCFF_X28_Y11_N17; Fanout = 2; REG Node = 'chuclkout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.173 ns" { keyclkout chuclkout } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.000 ns) 7.631 ns chuclkout~clkctrl 4 COMB CLKCTRL_G7 13 " "Info: 4: + IC(1.423 ns) + CELL(0.000 ns) = 7.631 ns; Loc. = CLKCTRL_G7; Fanout = 13; COMB Node = 'chuclkout~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.423 ns" { chuclkout chuclkout~clkctrl } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.932 ns) + CELL(0.666 ns) 9.229 ns outled\[1\]~reg0 5 REG LCFF_X17_Y15_N9 2 " "Info: 5: + IC(0.932 ns) + CELL(0.666 ns) = 9.229 ns; Loc. = LCFF_X17_Y15_N9; Fanout = 2; REG Node = 'outled\[1\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { chuclkout~clkctrl outled[1]~reg0 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 40.05 % ) " "Info: Total cell delay = 3.696 ns ( 40.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.533 ns ( 59.95 % ) " "Info: Total interconnect delay = 5.533 ns ( 59.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.229 ns" { inclk keyclkout chuclkout chuclkout~clkctrl outled[1]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.229 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} outled[1]~reg0 {} } { 0.000ns 0.000ns 0.975ns 2.203ns 1.423ns 0.932ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.025 ns + Longest register pin " "Info: + Longest register to pin delay is 7.025 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns outled\[1\]~reg0 1 REG LCFF_X17_Y15_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y15_N9; Fanout = 2; REG Node = 'outled\[1\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { outled[1]~reg0 } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.799 ns) + CELL(3.226 ns) 7.025 ns outled\[1\] 2 PIN PIN_69 0 " "Info: 2: + IC(3.799 ns) + CELL(3.226 ns) = 7.025 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'outled\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.025 ns" { outled[1]~reg0 outled[1] } "NODE_NAME" } } { "temp.vhd" "" { Text "F:/alter/2sfenpin/jianpan/zuihou/temp.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.226 ns ( 45.92 % ) " "Info: Total cell delay = 3.226 ns ( 45.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.799 ns ( 54.08 % ) " "Info: Total interconnect delay = 3.799 ns ( 54.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.025 ns" { outled[1]~reg0 outled[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.025 ns" { outled[1]~reg0 {} outled[1] {} } { 0.000ns 3.799ns } { 0.000ns 3.226ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.229 ns" { inclk keyclkout chuclkout chuclkout~clkctrl outled[1]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.229 ns" { inclk {} inclk~combout {} keyclkout {} chuclkout {} chuclkout~clkctrl {} outled[1]~reg0 {} } { 0.000ns 0.000ns 0.975ns 2.203ns 1.423ns 0.932ns } { 0.000ns 1.090ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.025 ns" { outled[1]~reg0 outled[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.025 ns" { outled[1]~reg0 {} outled[1] {} } { 0.000ns 3.799ns } { 0.000ns 3.226ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}