dis_control.vhd

一个计时器程序

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:30:25 11/12/2008 
-- Design Name: 
-- Module Name:    dis_control - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dis_control is
    
	 generic(divide_to_500k:integer:=100);
	 Port ( Clk : in  STD_LOGIC;
           Pick_up : in  STD_LOGIC;
           on_off	:	in	STD_LOGIC;
			  c_rst	:	in STD_LOGIC;
           Res		:	in	STD_LOGIC;
			  LCD_E : out  STD_LOGIC;
           LCD_RS : out  STD_LOGIC;
           LCD_RW : out  STD_LOGIC;
           Data_out : out  STD_LOGIC_VECTOR (3 downto 0));

end dis_control;

architecture Behavioral of dis_control is

signal	clk_2us	:	std_logic;
signal	Pick_up_tmp	:	std_logic;
signal	Data_in_tmp	:	std_logic_vector(7 downto 0);
signal	Code_in_tmp	:	std_logic_vector(7 downto 0);

type	state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);
signal	current_s	:	state:=s0;

type	code_buffer is array(0 to 13) of std_logic_vector(3 downto 0);
constant code_buf		:	code_buffer:=(x"3",x"3",x"3",x"2",x"2",x"8",x"0",x"6",x"0",x"f",x"0",x"1",x"0",x"1");

type	data_buffer is array(0 to 15) of std_logic_vector(7 downto 0);
constant	data_buf		:	data_buffer:=(x"57",x"65",x"6c",x"63",x"6f",x"6d",x"65",x"20",
												  x"54",x"6f",x"20",x"46",x"50",x"47",x"41",x"21");

signal	clk_1s	:	std_logic:='0';
signal	clk_1s_tmp	:	std_logic:='0';

signal	min_high	:	integer	range 0 to 9:=0;
signal	min_low	:	integer	range 0 to 9:=0;
signal	sec_high	:	integer	range 0 to 9:=0;
signal	sec_low	:	integer	range 0 to 9:=0;
signal	dis_encoder	:	integer	range 0 to 9:=0;

signal	dis_decoder	:	std_logic_vector(7 downto 0):=x"00";

begin

--process(Clk)
--
--variable	cnt_down_fre	:	integer	range 0 to divide_to_500k/2;
--
--	begin
--	if(Clk'event and Clk='1')then
--		if cnt_down_fre=(divide_to_500k/2-1)then
--			cnt_down_fre:=0;
--			clk_2us<=not clk_2us;
--		else
--			cnt_down_fre:=cnt_down_fre+1;
--		end if;
--	end if;
--
--end process;

clk_2us<=Clk;

process(clk_2us)

variable	cnt:			integer range	0 to 1000000;          --用于延时
variable	cnt_w:		integer range	0 to 100;
variable	cnt_code:	integer range	0 to 20;
variable	cnt_data:	integer range	0 to 20;
variable cnt_dis:		integer range	0 to 15;

	begin
	if(clk_2us'event and clk_2us='1')then
		if(Res='1')then
			current_s<=s0;
			cnt:=0;
			cnt_w:=0;
			cnt_code:=0;
			cnt_data:=0;
			cnt_dis:=0;
		else
			case current_s is
			
--------------------------------------------------------------------------------------------
--------------- LCD display initialization begin -------------------------------------------
--------------------------------------------------------------------------------------------			
			
			when s0=> LCD_RS<='1';						--延时30ms
						 LCD_RW<='1';
						 LCD_E<='0';
						 cnt:=cnt+1;
						 if cnt=15000 then
							cnt:=0;
							current_s<=s1;
						 end if;
			when s1=> cnt_w:=cnt_w+1;					--建立数据接口的指令
						 if cnt_w<3 then
							LCD_RS<='0';
							LCD_RW<='0';
							Data_out<=code_buf(cnt_code);
						 elsif cnt_w<7 then
							LCD_E<='1';
							 elsif cnt_w<8 then
								LCD_E<='0';
								  elsif cnt_w=8 then
									 cnt_w:=0;
									 cnt_code:=cnt_code+1;
									 case cnt_code is
									 when 1=>current_s<=s2;
									 when 2=>current_s<=s3;
									 when others =>current_s<=s4;
									 end case;
						 end if;

			when s2=> cnt:=cnt+1;					--延时10ms
						 if cnt=5000 then
							cnt:=0;
							current_s<=s1;
						 end if;
						 
			when s3=> cnt:=cnt+1;					--延时200us
						 if cnt=100 then
							cnt:=0;
							current_s<=s1;
						 end if;
			
			when s4=> cnt:=cnt+1;					--延时100us
						 if cnt=50 then
							cnt:=0;
							if cnt_code<4 then
								current_s<=s1;
							elsif cnt_code<12 then
								current_s<=s5;
								elsif cnt_code<16 then
									current_s<=s7;
									else
										current_s<=s12;
							end if;
						 end if;
			
			when s5=> Code_in_tmp(7 downto 4)<=code_buf(cnt_code);				--display config
						 Code_in_tmp(3 downto 0)<=code_buf(cnt_code+1);
						 cnt_code:=cnt_code+2;
						 current_s<=s6;
						 
			when s6=> cnt_w:=cnt_w+1;														 
						if cnt_w<3 then
							LCD_RS<='0';
							LCD_RW<='0';
							Data_out<=Code_in_tmp(7 downto 4);
						 elsif cnt_w<7 then
							LCD_E<='1';
							 elsif cnt_w<8 then
								LCD_E<='0';
								  elsif cnt_w<10 then                  --两组数据之间间隔4us
									  Data_out<=Code_in_tmp(3 downto 0);
									  elsif cnt_w<14 then
										  LCD_E<='1';
										  elsif cnt_w<15 then
											  LCD_E<='0';
											  elsif cnt_w=15 then
												 cnt_w:=0;
												 current_s<=s4;
						  end if;

			when s7=> cnt:=cnt+1;						--用于清屏后延时4ms
						 if cnt=2000 then
							cnt:=0;
							if cnt_code<14 then
								current_s<=s8;
							elsif cnt_code=14 then
								cnt_code:=20;
								current_s<=s12;
							end if;
						 end if;
			
--------------------------------------------------------------------------------------------
--------------- LCD display initialization over --------------------------------------------
--------------------------------------------------------------------------------------------
			
--------------------------------------------------------------------------------------------
-------------------- welcome information ---------------------------------------------------
--------------------------------------------------------------------------------------------

			when s8=> Data_in_tmp<=data_buf(cnt_data);			--display "Welcome To FPGA!"
						 cnt_data:=cnt_data+1;
						 current_s<=s9;
			
			when s9=> cnt_w:=cnt_w+1;									
						 if cnt_w<3 then
							LCD_RS<='1';
							LCD_RW<='0';
							Data_out<=Data_in_tmp(7 downto 4);
						 elsif cnt_w<7 then
							LCD_E<='1';
							 elsif cnt_w<8 then
								LCD_E<='0';
								  elsif cnt_w<10 then                  --两组数据之间间隔4us
									  Data_out<=Data_in_tmp(3 downto 0);
									  elsif cnt_w<14 then
										  LCD_E<='1';
										  elsif cnt_w<15 then
											  LCD_E<='0';
											  elsif cnt_w=15 then
												 cnt_w:=0;
												 current_s<=s10;
						  end if;
						  
			when s10=> cnt:=cnt+1;                                --延时100us
						 if cnt=50 then
							cnt:=0;
							if cnt_data<16 then
								current_s<=s8;
							elsif cnt_data=16 then
								cnt_data:=20;
								current_s<=s11;
								--延时后清屏
								else
									current_s<=s12;
							end if;
						 end if;
			
			when s11=> cnt:=cnt+1;
						  if(cnt=100)then							--delay for 2s/1000000
							cnt:=0;
							current_s<=s5;
							--clear display
						  end if;

---------------------------------------------------------------------------------------------------
---------------------- welcome information over ---------------------------------------------------
---------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------
---------------------- counter working display ----------------------------------------------------
---------------------------------------------------------------------------------------------------

			
			when s12=> cnt_dis:=cnt_dis+1;
						  case cnt_dis is
						  
						  when 1 =>Code_in_tmp<=x"25";						--locate at "05"
									  current_s<=s6;
						  when 2 =>dis_encoder<=min_high;
									  current_s<=s13;
						  when 3 =>Data_in_tmp<=dis_decoder;
									  current_s<=s9;
						  when 4 =>dis_encoder<=min_low;
									  current_s<=s13;
						  when 5 =>Data_in_tmp<=dis_decoder;
									  current_s<=s9;
						  when 6 =>Data_in_tmp<=x"3a";
									  current_s<=s9;
						  when 7 =>dis_encoder<=sec_high;
									  current_s<=s13;
						  when 8 =>Data_in_tmp<=dis_decoder;
									  current_s<=s9;
						  when 9 =>dis_encoder<=sec_low;
									  current_s<=s13;
						  when 10=>Data_in_tmp<=dis_decoder;
									  current_s<=s9;
						  when others =>cnt_dis:=0;
											 current_s<=s14;
						  end case;
			
			when s13=> case dis_encoder is
						  
						  when 0 =>dis_decoder<=x"30";
						  when 1 =>dis_decoder<=x"31";
						  when 2 =>dis_decoder<=x"32";
						  when 3 =>dis_decoder<=x"33";
						  when 4 =>dis_decoder<=x"34";
						  when 5 =>dis_decoder<=x"35";
						  when 6 =>dis_decoder<=x"36";
						  when 7 =>dis_decoder<=x"37";
						  when 8 =>dis_decoder<=x"38";
						  when 9 =>dis_decoder<=x"39";
						  when others =>dis_decoder<=x"30";
						  
						  end case;
						  current_s<=s12;
			
			when s14=> clk_1s_tmp<=clk_1s;
						  if(clk_1s_tmp='0' and clk_1s='1')then
			--			  if(clk_1s='1')then
								current_s<=s12;
						  end if;
						  
--			when s15=> Pick_up_tmp<=Pick_up;
--						 if(Pick_up_tmp='0' and Pick_up='1')then
--							Data_in_tmp<=Data_in;
--							current_s<=s8;
--						 end if;
			
			when others=> current_s<=s0;
			
			end case;
		end if;
	end if;

end process;

process(clk_2us)

variable	cnt_down_fre_to_1s	:	integer	range 0 to 250000;

	begin
	if(clk_2us'event and clk_2us='1')then
		if cnt_down_fre_to_1s=999 then             --for simulation 1000/250000
			cnt_down_fre_to_1s:=0;
			clk_1s<=not clk_1s;
		else
			cnt_down_fre_to_1s:=cnt_down_fre_to_1s+1;
		end if;
	end if;

end process;

process(clk_1s,c_rst,on_off)

	begin
	if(c_rst='0')then
		if(on_off='0')then
			if(clk_1s'event and clk_1s='1')then
				if(sec_low=9)then
					if(sec_high=5)then
						if(min_low=9)then
							if(min_high=5)then
								min_high<=0;
								min_low<=0;
								sec_high<=0;
								sec_low<=0;
							else
								min_high<=min_high+1;
								min_low<=0;
								sec_high<=0;
								sec_low<=0;
							end if;
						else
							min_low<=min_low+1;
							sec_high<=0;
							sec_low<=0;
						end if;
					else
						sec_high<=sec_high+1;
						sec_low<=0;
					end if;
				else
					sec_low<=sec_low+1;
				end if;
			end if;
		end if;
	else
		sec_low<=0;
		sec_high<=0;
		min_low<=0;
		min_high<=0;
	end if;
		
end process;	
	
end Behavioral;