📄 s3c44b0x.s
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PCOND_Val EQU 0x00000000
PUPD_Val EQU 0x00000000
;// <e> Port E
;// <o1.0..1> PE0 <0=> Input <1=> Output <2=> Fpllo <3=> Fout
;// <o1.2..3> PE1 <0=> Input <1=> Output <2=> TxD0 <3=> Reserved
;// <o1.4..5> PE2 <0=> Input <1=> Output <2=> RxD0 <3=> Reserved
;// <o1.6..7> PE3 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
;// <o1.8..9> PE4 <0=> Input <1=> Output <2=> TOUT1 <3=> TCLK
;// <o1.10..11> PE5 <0=> Input <1=> Output <2=> TOUT2 <3=> TCLK
;// <o1.12..13> PE6 <0=> Input <1=> Output <2=> TOUT3 <3=> VD6
;// <o1.14..15> PE7 <0=> Input <1=> Output <2=> TOUT4 <3=> VD7
;// <o1.16..17> PE8 <0=> Input <1=> Output <2=> CODECLK <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PE0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PE1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PE2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PE3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PE4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PE5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PE6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PE7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PE8 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOE_SETUP EQU 1
PCONE_Val EQU 0x00000000
PUPE_Val EQU 0x00000000
;// <e> Port F
;// <o1.0..1> PF0 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
;// <o1.2..3> PF1 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
;// <o1.4..5> PF2 <0=> Input <1=> Output <2=> nWAIT <3=> Reserved
;// <o1.6..7> PF3 <0=> Input <1=> Output <2=> nXBACK <3=> nXDACK0
;// <o1.8..9> PF4 <0=> Input <1=> Output <2=> nXBREQ <3=> nXDREQ0
;// <o1.10..12> PF5 <0=> Input <1=> Output <2=> nRTS1 <3=> SIOTxD
;// <4=> IISLRCK <5=> Reserved <6=> Reserved <7=> Reserved
;// <o1.13..15> PF6 <0=> Input <1=> Output <2=> TxD1 <3=> SIORDY
;// <4=> IISDO <5=> Reserved <6=> Reserved <7=> Reserved
;// <o1.16..18> PF7 <0=> Input <1=> Output <2=> RxD1 <3=> SIORxD
;// <4=> IISDI <5=> Reserved <6=> Reserved <7=> Reserved
;// <o1.19..21> PF8 <0=> Input <1=> Output <2=> nCTS1 <3=> SIOCLK
;// <4=> IISCLK <5=> Reserved <6=> Reserved <7=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PF0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PF1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PF2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PF3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PF4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PF5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PF6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PF7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PF8 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOF_SETUP EQU 1
PCONF_Val EQU 0x00000000
PUPF_Val EQU 0x00000000
;// <e> Port G
;// <o1.0..1> PG0 <0=> Input <1=> Output <2=> VD4 <3=> EINT0
;// <o1.2..3> PG1 <0=> Input <1=> Output <2=> VD5 <3=> EINT1
;// <o1.4..5> PG2 <0=> Input <1=> Output <2=> nCTS0 <3=> EINT2
;// <o1.6..7> PG3 <0=> Input <1=> Output <2=> nRTS0 <3=> EINT3
;// <o1.8..9> PG4 <0=> Input <1=> Output <2=> IISCLK <3=> EINT4
;// <o1.10..11> PG5 <0=> Input <1=> Output <2=> IISDI <3=> EINT5
;// <o1.12..13> PG6 <0=> Input <1=> Output <2=> IISDO <3=> EINT6
;// <o1.14..15> PG7 <0=> Input <1=> Output <2=> IISLRCK <3=> EINT7
;// <h> Pull-up Resistors
;// <o2.0> PG0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PG1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PG2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PG3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PG4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PG5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PG6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PG7 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOG_SETUP EQU 1
PCONG_Val EQU 0x00000000
PUPG_Val EQU 0x00000000
;// <e> Special Pull-up
;// <o1.0> SPUCR0: DATA[7:0] Pull-up Resistor
;// <0=> Enabled <1=> Disabled
;// <o1.1> SPUCR1: DATA[15:8] Pull-up Resistor
;// <0=> Enabled <1=> Disabled
;// <o1.2> HZ@STOP
;// <0=> Prevoius state of PAD
;// <1=> HZ @ Stop
;// </e>
PSPU_SETUP EQU 1
SPUCR_Val EQU 0x00000004
;// </e>
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors
b ResetHandler ;/* for debug */
b HandlerUndef ;/* handlerUndef */
b HandlerSWI ;/* SWI interrupt handler*/
b HandlerPabort ;/* handlerPAbort */
b HandlerDabort ;/* handlerDAbort */
b . ;/* handlerReserved */
ldr pc, =HandlerIRQ
b HandlerFIQ
IF VIM_SETUP <> 0
VECTOR_BRANCH ldr pc, =HandlerEINT0 ;/*mGA H/W interrupt vector table */
ldr pc, =HandlerEINT1 ;/* */
ldr pc, =HandlerEINT2 ;/* */
ldr pc, =HandlerEINT3 ;/* */
ldr pc, =HandlerEINT4567 ;/* */
ldr pc, =HandlerTICK ;/*mGA */
b .
b .
ldr pc, =HandlerZDMA0 ;/*mGB */
ldr pc, =HandlerZDMA1 ;/* */
ldr pc, =HandlerBDMA0 ;/* */
ldr pc, =HandlerBDMA1 ;/* */
ldr pc, =HandlerWDT ;/* */
ldr pc, =HandlerUERR01 ;/*mGB */
b .
b .
ldr pc, =HandlerTIMER0 ;/*mGC */
ldr pc, =HandlerTIMER1 ;/* */
ldr pc, =HandlerTIMER2 ;/* */
ldr pc, =HandlerTIMER3 ;/* */
ldr pc, =HandlerTIMER4 ;/* */
ldr pc, =HandlerTIMER5 ;/*mGC */
b .
b .
ldr pc, =HandlerURXD0 ;/*mGD */
ldr pc, =HandlerURXD1 ;/* */
ldr pc, =HandlerIIC ;/* */
ldr pc, =HandlerSIO ;/* */
ldr pc, =HandlerUTXD0 ;/* */
ldr pc, =HandlerUTXD1 ;/*mGD */
b .
b .
ldr pc, =HandlerRTC ;/*mGKA */
b . ;/* */
b . ;/* */
b . ;/* */
b . ;/* */
b . ;/*mGKA */
b .
b .
ldr pc,=HandlerADC ;/*mGKB */
ENDIF
HandlerFIQ ;HANDLER HandleFIQ
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleFIQ
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerIRQ ;HANDLER HandleIRQ
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleIRQ
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerUndef ;HANDLER HandleUndef
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleUndef
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerSWI ;HANDLER HandleSWI
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleSWI
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerDabort ;HANDLER HandleDabort
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleDabort
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerPabort ;HANDLER HandlePabort
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandlePabort
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerADC
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleADC
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerRTC
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleRTC
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerUTXD1 ; HANDLER HandleUTXD1
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleUTXD1
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerUTXD0 ;HANDLER HandleUTXD0
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleUTXD0
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerSIO ;HANDLER HandleSIO
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleSIO
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerIIC ;HANDLER HandleIIC
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleIIC
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerURXD1 ;HANDLER HandleURXD1
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleURXD1
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerURXD0 ;HANDLER HandleURXD0
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleURXD0
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerTIMER5 ;HANDLER HandleTIMER5
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleTIMER5
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerTIMER4 ;HANDLER HandleTIMER4
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleTIMER4
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerTIMER3 ;HANDLER HandleTIMER3
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleTIMER3
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerTIMER2 ;HANDLER HandleTIMER2
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleTIMER2
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerTIMER1 ;HANDLER HandleTIMER1
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleTIMER1
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerTIMER0 ;HANDLER HandleTIMER0
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleTIMER0
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerUERR01 ;HANDLER HandleUERR01
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleUERR01
ldr r9, [r8 ]
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