📄 seg.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity seg is
port( leddis: out std_logic_vector(7 downto 0);
disin: in integer range 0 to 9);
procedure led(num: integer range 0 to 9) is
begin
case num is
when 0=>
leddis<="00111111";
when 1=>
leddis<="00000110";
when 2=>
leddis<="01011011";
when 3=>
leddis<="01001111";
when 4=>
leddis<="01100110";
when 5=>
leddis<="01101101";
when 6=>
leddis<="01111101";
when 7=>
leddis<="00000111";
when 8=>
leddis<="01111111";
when 9=>
leddis<="01101111";
end case;
end led;
end seg;
architecture segarchi of seg is
begin
if disin<10 then
led(disin);
end if;
end segarchi;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -