📄 adringup.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity adringup is
port( reset: in std_logic;
bsset: in std_logic; --正点报时功能。
alarm: out std_logic;
hourhdis: in integer range 0 to 2;
hourldis: in integer range 0 to 9;
minhdis: in integer range 0 to 5;
minldis: in integer range 0 to 9;
sechdis: in integer range 0 to 5;
secldis: in integer range 0 to 9);
end adringup;
architecture adruarchi of adringup is --这块部分能够改进,增加功能。
constant rt: integer:=5;
constant stop: integer:=2;
begin
process(secldis)
variable cnt: integer;
variable bnt: integer;
begin
cnt:=sechdis*10+secldis;
bnt:=secldis;
if reset='1' then
alarm<='0';
elsif bsset='0' then
if (hourhdis=0 and hourldis=6 and minhdis=0 and minldis=0 and sechdis<2) or
(hourhdis=1 and hourldis=0 and minhdis=30 and minldis=0 and sechdis<2) then
if cnt<rt then --第一次响铃
alarm<='1';
elsif cnt>=rt and cnt<rt+stop then
alarm<='0';
elsif cnt<2*rt+stop then --第二次响铃
alarm<='1';
end if;
end if;
elsif (minhdis=0 and minldis=0 and sechdis=0 and secldis=0 and secldis<6) then
alarm<='1';
end if;
end process;
end adruarchi;
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