📄 timeset.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity timeset is
port ( reset: in std_logic; --系统复位信号
begend: in std_logic;
keyup: in std_logic;
enter: in std_logic;
settime: out std_logic;
hourhset: out integer range 0 to 2;
hourlset: out integer range 0 to 9;
minhset: out integer range 0 to 5;
minlset: out integer range 0 to 9;
sechset: out integer range 0 to 5;
seclset: out integer range 0 to 9);
end timeset;
architecture tsarchi of timeset is
type state is (sethh,sethl,setmh,setml,setsh,setsl,ini);
signal adjsta: state;
signal setmark: std_logic;
signal seclow,minlow,hourlow: integer range 0 to 9;
signal sechigh,minhigh: integer range 0 to 5;
signal hourhigh: integer range 0 to 2;
begin
seclset<=seclow;
sechset<=sechigh;
minlset<=minlow;
minhset<=minhigh;
hourlset<=hourlow;
hourhset<=hourhigh;
settime<=setmark;
mark: --???????????????????????????????
process(begend)
begin
if reset='1' then
setmark<='0';
elsif begend'event and begend='1' then
if setmark='1' then
setmark<='0';
else
setmark<='1';
end if;
end if;
end process;
normal_run:
process(enter,reset)
begin
if reset='1' then
adjsta<=ini;
elsif enter='1' and enter'event then
case adjsta is
when ini=>
adjsta<=sethh;
when sethh=>
adjsta<=sethl;
when sethl=>
adjsta<=setmh;
when setmh=>
adjsta<=setml;
when setml=>
adjsta<=setsh;
when setsh=>
adjsta<=setsl;
when setsl=>
adjsta<=sethh; --时间设置位循环
end case;
end if;
end process;
time_adjust:
process(keyup)
begin
if reset='1' then
hourhigh<=0;
hourlow<=0;
minhigh<=0;
minlow<=0;
sechigh<=0;
seclow<=0;
elsif keyup='1' and keyup'event then
case adjsta is
when sethh=>
hourhigh<=hourhigh+1;
when sethl=>
hourlow<=hourlow+1;
when setmh=>
minhigh<=minhigh+1;
when setml=>
minlow<=minlow+1;
when setsh=>
sechigh<=sechigh+1;
when setsl=>
seclow<=seclow+1;
when ini=>
NULL;
end case;
end if;
end process;
end tsarchi;
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