📄 display.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity display is
port( sclk: in std_logic;
reset: in std_logic;
secdis: out std_logic_vector(7 downto 0);
addsel: out std_logic_vector(2 downto 0);
hourhdis: in integer range 0 to 2;
hourldis: in integer range 0 to 9;
minhdis: in integer range 0 to 5;
minldis: in integer range 0 to 9;
sechdis: in integer range 0 to 5;
secldis: in integer range 0 to 9);
procedure leddisp(number: integer range 0 to 9) is
begin
case number is
when 0=>
secdis<="00111111";
when 1=>
secdis<="00000110";
when 2=>
secdis<="01011011";
when 3=>
secdis<="01001111";
when 4=>
secdis<="01100110";
when 5=>
secdis<="01101101";
when 6=>
secdis<="01111101";
when 7=>
secdis<="00000111";
when 8=>
secdis<="01111111";
when 9=>
secdis<="01101111";
end case;
end leddisp;
end display;
architecture dparchi of display is
type state is (s1,s2,s3,s4,s5,s6);
signal nexsta,cursta: state;
begin
scan:
process(sclk)
begin
if reset='1' then
nexsta<=s1;
elsif (sclk='1' and sclk'event) then
cursta<=nexsta;
end if;
case cursta is
when s1=>
addsel<="000";
leddisp(hourhdis);
nexsta<=s2;
when s2=>
addsel<="001";
leddisp(hourldis);
nexsta<=s3;
when s3=>
addsel<="010";
leddisp(minhdis);
nexsta<=s4;
when s4=>
addsel<="011";
leddisp(minldis);
nexsta<=s5;
when s5=>
addsel<="100";
leddisp(sechdis);
nexsta<=s6;
when s6=>
addsel<="101";
leddisp(secldis);
nexsta<=s1;
when others=>
null;
end case;
end process;
end dparchi;
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